NXP announces availability of CGV high speed converter demo boards based on LatticeECP3 FPGAs

EINDHOVEN, THE NETHERLANDS: NXP Semiconductors announced the availability of two low cost, low power demonstration boards for its CGV high speed data converter family, based on the Lattice Semiconductor LatticeECP3 FPGA.

The demo boards are designed to demonstrate the interoperability of NXP‘s CGV converters with Lattice‘s ECP3 FPGA family. One demo board features the NXP ADC1413D and the Lattice ECP3 device, while the other board features the NXP DAC1408D and the LatticeECP3 device.

NXP will demonstrate the ADC1413D demo board at the IEEE Microwave Theory and Techniques Society (MTT-S) / International Microwave Symposium (IMS) Conference in Anaheim, California from May 25-27. NXP‘s booth number is 3324.

The NXP CGV high speed data converters utilize an enhanced implementation of the JEDEC JESD204A standard serial interface. JESD204A dramatically reduces the number of interconnect signals between data converters and VLSI logic devices. It also solves the perplexing customer design challenge by allowing multiple data converter channels to be bonded synchronously.

“Lattice is pleased to have collaborated with NXP in the development of the new demo boards and in the interoperability testing of the JESD204A standard,” said Ron Warner, European marketing manager, Lattice Semiconductor. “Our ECP3 FPGA family provides the lowest cost and lowest power solution for system designers implementing the JESD204A in their applications.”

“NXP is pleased to offer the two new demo boards as a tangible evidence of interoperability and interworking of our new CGV converters with Lattice‘s ECP3 FPGAs,” said Maury Wood, product line manager, High Speed Converters, NXP Semiconductors. “Design engineers in applications ranging from base stations to high speed instrumentation can utilize this reference design as a starting point for their specific requirements.”

The new demo boards are USB powered, and can work together (with the DAC board output feeding the ADC board input) hosted by a single notebook computer with two spare USB ports running LabView or other signal analysis software.

CGV (Convertisseur Grande Vitesse) designates NXP‘s compliant, superset implementation of the JEDEC JESD204A interface standard, with a 28 percent increase in the transmitter rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps) and a 400 percent increase in the transmitter reach (up to 100 cm versus the standard reach of 20 cm).

The enhanced CGV features include Multi Device Synchronization (MDS) for the DAC1408D series of D/A Converters. NXP has implemented this optional feature to enable LTE MIMO base station and other advanced multi-channel applications. NXP‘s implementation of MDS enables up to sixteen DACs data streams to be sample synchronized and phase coherent.

The LatticeECP3 family is the third - generation, high - value FPGA from Lattice Semiconductor, which offers the industry‘s lowest power consumption and lowest price for any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.

The ADC1413D plus ECP3 demonstration board is available immediately. The DAC1408D plus ECP3 board will be available from September 2010. The price for both boards is $299 each.