Mentor Graphics receives TSMC’s partner of the year award for 3D-IC design enablement

WILSONVILLE, USA: Mentor Graphics Corp. announced it was chosen as a TSMC 2011 Partner of the Year for its role in 3D-IC design enablement. The Mentor and TSMC collaborations provide a robust flow for verifying multi-die system designs using silicon interposer integration techniques.

“Mentor has been our collaborator in physical verification for multiple nodes, and now that we are moving from single-die to multi-die systems, they continue to provide valuable contributions for new technology development,” said Suk Lee, director of Design Infrastructure Marketing at TSMC.

“We’re very pleased to receive this award, which demonstrates our commitment to continued innovation, providing our mutual customers with robust, production-ready tools ahead of general market requirements,” said Joseph Sawicki, VP and GM of Mentor Graphics Design-to-Silicon division.

The Calibre platform supports design rule checking (DRC), layout vs. schematic (LVS) checking and extraction of designs employing silicon interposer configurations using through silicon vias (TSVs). 3D-IC designs are supported with straightforward extensions, called the Calibre 3DSTACK, to the Calibre feature set so customers can incorporate the new technology with minimal changes to their existing design flows, using the same Calibre signoff decks they use for current 2D chip designs.

The Mentor Graphics Tessent silicon test product suite also supports comprehensive testing of 3D-IC designs. The Tessent tools support testing of interposer and 3D configurations with logic, stacked memory, embedded CPU cores, and Wide IO bus or high-speed serial I/O.