Latest Synopsys FPGA-based prototyping tool releases improve speed and turnaround time

MOUNTAIN VIEW, USA: Synopsys Inc. announced updates to its Identify and Certify FPGA-based prototyping tools. Algorithm advancements in the latest Certify software release produce up to 30 percent faster FPGA-to-FPGA transmission performance using High-Speed Time Domain Multiplexing (HSTDM), which results in higher overall performance of designs prototyped with Synopsys' HAPS FPGA-based prototyping systems.

The new Certify and Identify software tools also incorporate incremental compilation technology that accelerates implementation of design revisions, as well as automation to ease the partitioning of large designs into multiple HAPS boards.

"The new Certify and Identify releases offer significant productivity gains and faster performance for ASIC prototyping engineers," said Wouter Suverkropp, product line marketing manager of Virtex-6 FPGAs at Xilinx. "When used with Synopsys' HAPS-60 series systems that can support up to 81 million ASIC gates, these releases are well suited to make the most of the powerful Virtex-6 LX760 devices that each provide 760,000 logic cell capacity, 26Mbits of internal memory, and 864 DSP blocks."

Certify multi-FPGA ASIC prototyping software delivers higher performance
The latest release of the Certify multi-FPGA ASIC prototyping software incorporates new and enhanced features for higher prototype performance and greater ease of use with Synopsys' HAPS systems, allowing designers to:

* Increase the data throughput of prototypes enabled by up to 30 percent faster HSTDM of I/Os.
* Quickly bring-up prototypes built with multiple HAPS boards using system target Tcl scripting.
* Produce very accurate static timing analysis estimates with post-route delay back annotation.
* Speed ASIC design migration with support for encrypted DesignWare Library IP.
* Obtain a more complete resource analysis of multi-FPGA designs with new PCB trace impact analysis.

Identify RTL debugger enhances visibility and turnaround time
A high degree of visibility inside the FPGAs of the prototyping system significantly improves debugging efficiency. The latest release of Identify RTL debugger includes new and enhanced capabilities that improve debug throughout the design cycle and reduce turnaround time, allowing designers to:

* Understand prototype operation faster with debugger results annotated in the RTL View of the Synplify HDL Analyst graphical analysis tool.
* Isolate defects by tracing longer periods of signal activity with up to 64 times more sample buffer capacity Update and implement design instrumentation faster with Synplify compile point technology by preserving design modules not affected by debug instrumentation.

Both software tools are designed for use with Synopsys' HAPS systems, though enhancements in these latest tool releases also benefit custom and build-your-own prototypers.

"As design complexity grows, it is increasingly important for developers to prototype their designs quickly and debug them efficiently," says Ed Bard, senior director of product marketing at Synopsys. "The new Identify and Certify tool releases include significant advancements in the FPGA software tool flow that directly translate to higher productivity for our HAPS users, and also ensure that designers who build their own hardware prototypes can do so faster and with less effort."