Analog Bits accelerates analog IP verification using Magma’s FineSim SPICE

SAN JOSE, USA: Magma Design Automation Inc. announced that Analog Bits, Inc., the integrated clocking and interface IP leader, accelerates analog IP verification for its precision clocking macros, programmable interconnect solutions and specialized memories using FineSim SPICE multi-CPU circuit simulation technology.

Using the FineSim SPICE multi-CPU simulation technology, Analog Bits has significantly shortened simulation runtimes, increasing simulation coverage without sacrificing accuracy.

“We’ve found FineSim SPICE an excellent match for our advanced mixed-signal design environment,” said Mahesh Tirupattur, executive VP of Analog Bits. “We’ve achieved a 10X productivity boost over our traditional SPICE simulator with FineSim SPICE, allowing us to improve simulation coverage and to deliver higher quality analog IP faster.”

“The market adoption of FineSim is growing rapidly, over 100 companies are now using it in their design flows,” said Anirudh Devgan, general manager of Magma’s Custom Design Business Unit. “Many FineSim users are reporting impressive productivity improvements, underscoring the software’s ability to simulate tough analog designs fast.”

FineSim SPICE
FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-signal and analog designs. FineSim SPICE is a full SPICE simulation engine with distributed processing that enables customers to simulate large-scale mixed-signal system chips at the transistor level.

By providing increased speed and capacity while maintaining full SPICE accuracy, FineSim SPICE enables designers to simulate advanced circuits – such as PLLs, ADCs (analog-to-digital converters), DACs (digital-to-analog converters) and gigahertz SERDES (SERializer/DESerializer) – that they previously would not even attempt using slower traditional SPICE simulators.