TOULOUSE, FRANCE: DMAP, a company focused on high reliability semiconductor applications and producing DO-254 compliant IP, has made available to the market PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog and Assertion Based Verification (ABV) in an OVM environment.
Adherence to DO-254 compliance during development, and verified using advanced verification methods supported by Mentor Graphics industry-leading Questa functional verification platform, ensures thorough testing of these complex IP devices.
DO-254 explicitly requires functional coverage, a verification approach that ensures all requirements have been covered in the designed hardware. The DO-254 standard states the following: “Evidence is provided that the hardware implementation meets the requirements” [DO-254 6.2.1-1]. Regardless of the level of design (LRU, board, device, IP) and design assurance level (DAL) of the item, functional coverage is the fundamental metric of every ‘safe’ design flow.
Supplementing a requirements-driven approach to verification and functional coverage, HDL code coverage is also commonly used in DO-254 programs. While not explicitly mentioned in DO-254, code coverage is often used in support of elemental analysis, an advanced verification method described in DO-254 Appendix B to ensure that all the design elements have been exercised during verification. Newer regulatory policy has mandated the use of code coverage for DAL A and B digital hardware projects.
Specifically, the recent EASA CEH memo states”…an HDL code coverage measurement is an acceptable means to assess the way the HDL code has been exercised during device functional verification by simulation.” [EASA CM-SWCEH-001 22.214.171.124]. With Questa functional verification platform from Mentor Graphics, DMAP’s verification team has been able to reach 100 percent coverage on both hardware requirements (i.e., functional coverage) and HDL code (i.e., code coverage) in an automated way.
Quite straightforward, both functional and code goals are extracted from the document, which describes the verification procedures (HVCP) or verification‘s code (SV) then Questa simulator is able to automatically answer the question: Are we done?
“DMAP’s team is pioneering advanced verification techniques on DO-254 compliant IP” stated Michelle Lange, DO-254 program manager at Mentor Graphics. “It’s good to see these methods – which are used extensively in every other industry because they offer more efficient and higher quality results – being used now in an industry where the verification effectiveness is so crucial. DMAP, with their use of Questa and advanced methods, is demonstrating their leadership and understanding of the value of these methods in support of safety-critical design.”
“By using more modern verification techniques such as SystemVerilog, formal methods, ABV, and Bus Functional Models (BFMs), we are now able to reach all DO-254 goals on very high complex IP or FPGA designs in a short amount time and for a competitive cost,” said James Bezamat, CEO and DO-254 evangelist at DMAP.
Already available for DO-254 DAL A designs, our Generation One PCI Express Endpoint and 10/100/100 Ethernet MAC semiconductor IP products can be customized on request to match your needs. The DMAP’s product list also includes ARINC429 and CAN bus interface.