Arasan Chip Systems releases ONFI 3.0 NAND Flash controllers

SAN JOSE, USA: Arasan Chip Systems Inc., a leading provider of Intellectual Property (IP) Cores, announced the availability of NAND Flash Controllers supporting the newest Open NAND Flash Interface (ONFI) 3.0 specification.

The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development.

Designed to support SLC and MLC flash memories, it is flexible to use and implement. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, ST-Micro, and others.

Arasan's NAND Flash Controller support the fastest transfer modes up to 400MTS with differential signaling on clock and data, and double data-rate transfers (DDR) The IP incorporates all of the new features of ONFI 3.0 such as eight chip enables, page sizes up to 8K and ECC up to 64 bits with dynamic configuration, warm-up cycles. All ONFI 3.0 commands are supported and the controller is backwards compatible with earlier versions of ONFI.

The IP core supports the Open NAND Flash Interface Working Group (ONFI) 3.0 standard and is backward compatible. It uses differential signaling on the clock and data lines and clocks at any frequency up to 200 MHz.

Rapid development of new, high capacity NAND memory devices makes it the preferred non-volatile memory solution for a wide range of products from cell phones, consumer electronics to netbooks. However, this increase in capacity and performance of NAND memories is accompanied with corresponding increase in memory controller complexity.

Arasan's NAND Flash Controller is architected to handle growing raw error bit rates as NAND memory migrates to finer process geometries by processing information contained in the Extended ECC Information data structure stored in NAND memory. In addition, the controller supports booting directly from NAND memory. The IP core is implemented using a generic standard cell based flow combined with delay components that are part of a typical ASIC cell library. By integrating Arasan's NAND Flash Controller, SoC designers can interface to a variety of NAND memory devices via a standard ONFI interface.

"SoC designers would like to exploit advances in NAND memory technology without having to develop proprietary interfaces, thereby ensuring compatibility," said Prakash Kamath, VP of Engineering at Arasan. "With Arasan's NAND Flash controllers, designers can seamlessly interface to any ONFI 3.0 compliant memory, independent of the underlying NAND memory technology."

"Consumer and mobile device manufacturers are constantly exploring options to reduce the cost of their system solutions, particularly memory components," said Ron Mabry, VP of Sales at Arasan. "By integrating Arasan's NAND Flash Controller, they now have the option to integrate the most cost effective ONFI based memory over the life of the host processor."

Arasan provides a "Total IP Solution" for its NAND Flash Controller IP core consisting of RTL source code, synthesis scripts, test environment and documentation, all backed by Arasan's World-class customer support.