Synopsys announces availability of DesignWare PHY and embedded memory IP for TSMC advanced 28-nm technologies

MOUNTAIN VIEW, USA: Synopsys Inc. announced that it has worked with TSMC to develop a broad portfolio of DesignWare interface PHY IP including SuperSpeed USB 3.0, USB 2.0, HDMI, PCI Express, DDR and SATA as well as embedded memories for TSMC's 28-nanometer (nm) process technology. The collaboration enables designers to incorporate more functionality into their advanced system-on-chips (SoCs), while meeting low power and small silicon area requirements.

As a result of this collaboration, Synopsys has achieved USB logo certification for the DesignWare USB 2.0 picoPHY IP in TSMC's 28-nm process, demonstrating a robust design architecture that can withstand rigorous process, voltage and temperature variations.

In addition, the DesignWare IP portfolio of SiWare Embedded Memory SRAMs has also achieved positive silicon results for TSMC's 28-nm process. The longstanding cooperation between the two companies has resulted in the development of DesignWare PHY IP from 180-nm to 28-nm process technologies, allowing design teams to integrate key industry standard interfaces into their designs with less risk and improved time-to-market.

"TSMC's close relationship with Synopsys through the years has provided mutual customers access to a broad portfolio of high-quality IP solutions for a wide range of TSMC processes," said Suk Lee, director of Design Infrastructure Marketing Division, at TSMC. "Our collaboration with Synopsys on the development of DesignWare PHY and Embedded Memory IP for TSMC's advanced 28-nm process is a natural extension of our successful track record, and further demonstrates our shared commitment to delivering to designers widely-used SoC functionality for their high-performance, low power mobile designs."

"Synopsys' collaboration with TSMC has helped designers cope with the challenges of incorporating advanced interfaces into their SoCs," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing a broad portfolio of IP that has been silicon-proven to be robust in process, voltage and temperature variations for TSMC processes, we can continue to help customers reduce integration risk and speed their creation of differentiated SoCs."

The DesignWare PHY IP for the TSMC 28-nm process is scheduled to be available in Q2 of 2011. The DesignWare IP portfolio of SiWare Embedded Memories for the TSMC 28-nm process is available now.