Mentor Graphics teams with TSMC to enrich Reference Flow 11 low power verification solutions

WILSONVILLE, USA: Mentor Graphics Corp. announced it has expanded the use of low power verification capabilities in TSMC’s Reference Flow 11 to address today’s complex integrated circuit (IC) low power functional verification requirements. The Mentor low power verification tool suite includes the Questa functional verification platform, the 0-In CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro equivalence checking tool.

“Many design teams struggle with the functional verification of their designs where low power requirements put increased pressure to meet functional specifications,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Mentor continues to show a high degree of commitment to enhance the capabilities of their functional verification technologies, and considerable foresight to determine what new capabilities will be required in the years to come.”

“Low power requirements are a top priority for a majority of our mutual customers,” said John Lenyo, general manager, Mentor Graphics. “That’s why effective low power design verification solutions continue to be one of our top priorities, and we intend to extend our collaboration with TSMC on future reference flow programs.”

Low power functional verification
Power management has become one of the most critical issues in most digital chips and systems. Portable systems must maximize battery life and virtually all products must minimize heat generation. Active power management creates new challenges for chip design and verification because the chip must now function correctly even though at any given time some portions of it may not be powered up.

A comprehensive functional verification solution must verify not only the power management architecture, but also the power management control systems, while also verifying the underlying functionality of the design. The combination of the Questa functional verification platform, the 0-In CDC tool, the 0-In Formal tool and the FormalPro tool enables users to address all aspects of the low power verification problem.

The Questa functional verification platform supports power aware simulation of RTL and gate-level designs, including:

* Support of the Unified Power Format (IEEE P1801) for specification of power intent.
* Accurate modeling of power management architecture and control logic.
* Native implementation of UPF for high performance simulation.
* Automatic insertion of assertions to check for power management errors.
* Visualization and debug of power management behavior.

The FormalPro tool ensures that the power intent in the RTL design is maintained through the implementation, including:

* RTL-to-gate and gate-to-gate power aware equivalence checking.
* Native UPF language processing with full TCL 8.4 interpreter for multi-product UPF compatibility and user configurations.
* Liberty 2.5 library compatibility with Power+Ground (PG) netlist support for RTL-to-PG compare.
* Full schematic support for PG netlist exploration.

The 0-In Formal tool enables complete verification of active power management control structures, including:

* Automatic identification of design logic issues without assertions.
* Complete verification of power control unit logic and power control signal sequencing.

The 0-In CDC tool enables verification of complex clock domain crossings in low power design, including automatic identification of clock domains and synchronizers, formal and simulation-based CDC verification as well as automated metastability injection.