Silicon Valley startup granted US patent on critical DDR2/DDR3 timing innovation for chip designs

SANTA CLARA, USA: Uniquify, a Silicon Valley semiconductor IP start-up, announced that it has been granted a United States patent covering its innovative solution for designing DDR (double data rate) memory controllers that satisfy challenging timing requirements.

The company’s patented ‘Self-Calibrating Logic’ (SCL) permits SoC (system-on-chip) designs that use Uniquify’s memory controller IP (intellectual property) to automatically fine-tune critical timing parameters after the SoCs are installed in system boards.

Today’s deep sub-micron SoC designs integrate DDR memory controllers that operate at multi-GHz clock rates. At these clock rates, system-level memory read-write timing margins are measured in picoseconds. Designing DDR PHYs that satisfy these timing requirements can require exhaustive rounds of incremental IC design modifications, and the resulting silicon often fails to produce high yielding devices in high-volume production.

Uniquify’s memory controller IP, which incorporates its patented SCL technology, performs a system self-test on power-up that allows the controller’s PHY circuitry to automatically fine-tune timing parameters every time the host SoC is reset. Not only does SCL eliminate the need for excessive design tweaks to achieve timing closure during the SoC development stage, chips with SCL are much higher yielding due to their ability to automatically adapt their timing characteristics for a wide range of system-level design choices and for variations in the SoC foundry process.

“System level timing requirements are the most challenging part of memory controller design. Precise details about the system board design, the type of external memory devices used, and even details about the host SoC may not be finalized--or may not be well characterized--when the DDR PHY is initially designed,” explained Uniquify CEO and founder Josh Lee. “Our patented SCL technology allows Uniquify to move the final determination of exact timing parameters from the IC design stage to system power-on in the field, when all of the characteristics that affect timing are finalized and implemented.”