Saturday, July 31, 2010

Memory and foundry companies shine in 1H10 semiconductor ranking

SCOTTSDALE, USA: IC Insights' recently updated Strategic Reviews Online database shows that most large memory and foundry companies performed extremely well in 1H10. As shown in Fig. 1, most of these companies registered strong doubledigit growth rates in 2Q10/1Q10 to move up in the ranking.

Of the big five memory suppliers in the top 20 ranking (ie, Samsung, Toshiba, Hynix, Micron, and Elpida), all but Samsung gained at least one position (with Elpida jumping five spots to number 10).

Fig. 1Source: IC Insights, USA.

Although Samsung did not move up in the ranking, it did gain ground on the number one supplier—Intel. In 2009, Intel's semiconductor sales were 52 percent larger than Samsung's. However, in 2Q10, Intel's sales margin over Samsung was reduced by more than half, to only 21 percent!

It is no secret that the DRAM and NAND flash memory markets have been extremely strong over the past few quarters. This is very evident when looking at the 2Q10/1Q10 sales increases of Hynix (14 percent), Micron (14 percent), and Elpida (18 percent). Moreover, each of these companies 1H10 sales were only about $1 billion or less than their full-year 2009 sales results!

The two largest semiconductor foundries, TSMC and UMC, also did very well in the first half of 2010. As shown in Fig. 1, TSMC moved up one spot in the ranking to the 5th position, while UMC jumped six spots into 18th place!

If foundries were excluded from the top 20 ranking, Panasonic (1H10 sales of $1,830 million) and Nvidia (1H10 sales of $1,804 million) would claim the 19th and 20th positions, respectively.

Although Renesas and NEC did not officially merge until April 1, 2010, for ease of comparison, IC Insights combined the two companies' semiconductor sales for all of 2009 and 1Q10. As shown, the "new" Renesas went from being ranked 4th in 2009 to 6th in 1H10.

Collectively, the top 20 semiconductor companies had sales of about $102 billion in 1H10. If 2H10 sales are only flat with 1H10 (they will probably be higher), the total sales of the top 20 companies would be $204 billion. Even at $204 billion, the full-year 2010 top 20 sales growth rate would be 29 percent.

Source: IC Insights, USA.

Thursday, July 29, 2010

2010 to show largest semiconductor market increase in history!

SCOTTSDALE, USA: IC Insights' new 220-page Mid-Year Update to The McClean Report shows that the 2010 worldwide semiconductor market is forecast to register the largest dollar volume increase in history—$72 billion (to $310 billion total).

As shown in Fig. 1, the 2010 increase is expected to exceed the previous record high of $59 billion, set in 2000, by 22 percent.

The $72 billion increase in 2010 would equate to a growth rate of 30 percent over 2009. This 30 percent jump would be the sixth largest in the past 32 years and the highest since the 37 percent increase 10 years ago in 2000.

Fig. 1Source: IC Insights, USA.

A large percentage of the $72 billion 2010 semiconductor market increase is forecast to be quickly converted into a rush of capital spending by the semiconductor producers.

As detailed in The Mid-Year Update, 2010 semiconductor industry capital spending is expected to surge by $21.4 billion, an 83 percent jump over 2009 (to $47.2 billion total)! This $21.4 billion increase in capital spending represents 30 percent of the total semiconductor industry dollar volume growth forecast for this year.

Although worldwide GDP is forecast to grow by 3.9 percent in 2010, this growth rate is only 0.3 point above the long-term average rate of 3.6 percent. Thus, the real driving force behind the $72 billion semiconductor market increase this year is the extremely strong growth in the PC and smartphone segments.

In 2010, PC unit volume shipments are forecast to grow by at least 18 percent, to 338 million, with smartphone unit sales expected to surge by 21 percent to 275 million. Moreover, momentum is still building, with both segments forecast to register at least 10 percent higher unit volume shipments in the second half of this year as compared to the first half.

Source: IC Insights, USA.

Wednesday, July 28, 2010

Foxconn rides partnership with Apple to take 50 percent of EMS market in 2011

EL SEGUNDO, USA: Driven by fast growth at Apple Inc., leading Electronics Manufacturing Services (EMS) provider Foxconn Technology Group is set to take more than half of global EMS industry revenue by 2011, up from 44.2 percent in 2009, according to iSuppli Corp.

“Foxconn’s customers are some of the hottest companies in the electronics business today, most notably Apple Inc.,” said Thomas Dinges, iSuppli associate. “As Apple and others have gained share, so has Foxconn.”

The figure presents iSuppli’s ranking of the top 10 EMS providers in the first quarter based on revenue. EMS providers are defined as companies whose primary business is the contract manufacturing of electronic products on behalf of Original Equipment Manufacturers, or OEMs.Source: iSuppli, USA.

With revenue of $17.1 billion, Taiwan’s Foxconn, aka Hon Hai Precision Industries Ltd., was the dominant EMS provider in the first quarter of 2010, dwarfing No. 2 player Flextronics International Ltd., which posted revenue of $5.9 billion during the same period. Foxconn’s revenue in the first quarter surged 54.1 percent from $11.1 billion during the same period in 2009.

Part of Foxconn’s revenue boom is due to the industry wide strength of the digital consumer business and a strong recovery in computing-related products. Moreover, the company dramatically outperformed the 27.5 percent year-over-year revenue increase for the Top 10 EMS providers in the first quarter, reflecting the strength of its customer base.

Apple represents the fastest-growing customer for Foxconn, which manufactures products including the iPad and the iPhone 4.

iSuppli last week noted that Apple had issued increased production targets for the iPad to its Asian suppliers. iSuppli now predicts Apple will ship 12.9 million iPads in 2010 , an amount that will nearly triple to reach 36.5 million in 2011.

Meanwhile, global iPhone shipments are expected to rise to 53.5 million in 2011, more than double the 25.1 million in 2009.

To support this massive increase in production, Apple is ratcheting up its semiconductor purchasing. By 2011, Apple will become the world’s second-largest purchaser of semiconductors through direct and indirect channels. Indirect channels include purchases through EMS providers, such as Foxconn.

The fantastic Foxconn
With Foxconn controlling nearly 50 percent of EMS industry revenue, the company’s strong performance is driving the overall market. Company revenue increased by 3.4 percent in 2009, while the overall EMS industry contracted by 11.9 percent. Foxconn was the only Top 10 EMS provider to achieve annual growth in 2009.

The only negative for Foxconn is in its gross margin performance. Company gross margins dipped to 8.7 percent in the first quarter, down from 9.5 percent a year ago.
“Margins are a key area for Hon Hai, as the company is working to implement higher wage rates in its large facilities in China, while shifting production over the next several quarters to lower-cost regions in that country,” Dinges said.

The company invested heavily in inventory during the first quarter. Company inventory in the first quarter rose $400 million sequentially and was up $900 million compared to last year, in anticipation of strong demand as well as new product launches from customers such as Apple.

Source: iSuppli, USA.

Microsemi, Spelsberg in strategic alliance for disruptive solar bypass technology

IRVINE, USA: Microsemi Corp., a leading manufacturer of high performance analog/mixed signal integrated circuits and high reliability semiconductors, and Spelsberg, in conjunction with its partner, the Fraunhofer Institute for Solar Energy Systems ISE, announced the development of a disruptive new technology for photovoltaic (PV) solar modules.

The technology was demonstrated at InterSolar 2010, July 13-15, 2010, in San Francisco, California. Spelsberg ELS is a German based expert in connection systems for PV modules, and Fraunhofer ISE is the largest solar energy research institute in Europe.

Microsemi has worked with Spelsberg ELS and Fraunhofer ISE to develop a breakthrough solar bypass technology that significantly increases reliability while reducing power dissipation in the critical bypass diode by up to ninety percent as compared to today's typical solutions.

Microsemi products based on the technology will implement Microsemi's patented, ultra-low-power CoolRUN technology that enables increased power generation efficiency and significantly reduces operating temperatures while slashing the operational expense, reliability problems and associated warranty costs of traditional solutions using Schottky diodes.

"Microsemi is excited to bring this new, ground-breaking technology to the solar PV industry," said Paul Pickle, General Manager of Microsemi's Analog Mixed Signal Group.

"Our new solar bypass solution will be the first of its kind to address thermal reliability, operational cost and efficiency issues common in solar installations, which will enable improved profitability, a faster break-even time, and improved energy efficiency. Our successful demonstrations at the Photovoltaic Symposium in Bad Staffelstein, Germany, ASES National Solar Conference, and InterSolar shows in Munich and San Francisco are key steps toward deployment of this breakthrough technology."

"Spelsberg is pleased that our partnership with Microsemi has resulted in this breakthrough product offering," said Holger Spelsberg, MD. "We selected Microsemi for their expertise and experience developing solutions for the photovoltaic industry as well as high reliability, aerospace and satellite solutions. Our pooling of unique Microsemi and Spelsberg intellectual property enabled this groundbreaking development."

"We are pleased that Microsemi's new solar bypass solution leverages our system-level knowledge and intellectual property," said Dr. Heribert Schmidt of Fraunhofer ISE. "By combining Microsemi's IC design expertise with our knowledge of solar-energy scientific fundamentals, prototyping, and demonstration-system development, we have achieved a key milestone on the road to significantly more reliable and power-efficient PV modules."

Microsemi's newly developed technology will be used in solar modules for commercial, residential and industrial applications. The technology, in conjunction with Microsemi's high-reliability, 40-year design rule methodology will enable support for demanding industry warranty requirements and extreme environment survivability.

Microsemi and its partners believe that this breakthrough diode technology will have a particularly significant impact on the economic models of large-scale solar-energy providers in the power purchase agreement (PPA) market. The resulting reduction in thermal dissipation greatly improves reliability essential to solar powered systems' operational expenses and return on investment.

Xilinx improves design flow for industry's only proven partial reconfiguration FPGA technology with ISE Design Suite 12.2

SAN JOSE, USA: Xilinx Inc. has announced the availability of its fourth generation partial reconfiguration design flow and new improvements to its intelligent clock gating technology that deliver a 24 percent reduction in dynamic block-RAM (BRAM) power consumption in Virtex-6 FPGA designs.

Designers can download ISE Design Suite 12.2 today to take advantage of an easier-to-use, intuitive partial reconfiguration design flow as well as take further steps to reduce power consumption and reduce overall system costs. In addition, a low-cost simulation solution for the embedded design flow is also now available in the latest release of the ISE Design Suite.

"As systems become more complex and designers are asked to do more with less, the adaptability of FPGAs, in addition to their inherent reprogramability, has become a critical asset," said Tom Feist, senior marketing director, ISE Design Suite.

"Xilinx FPGAs have long supported partial reconfiguration and the flexibility to perform on-site programming and re-programming. Today, however, the severity of the constraints on cost, board space and power consumption requires exceptionally efficient and economic design strategies to compete, which is why we've made the design flow easier."

Partial Reconfiguration enables on-the-fly flexibility that can dramatically expand the capabilities of a single FPGA. While operational, designers can reprogram regions of the FPGA with new functionality without compromising the integrity of the applications running in the remainder of the device.

For example, customers developing wired Optical Transport Network solutions can achieve multi-port multiplexer/transponder capabilities using 30-45 percent fewer resources, whereas Software Defined Radio solutions can dynamically exchange communication waveforms at the same time as other waveforms continue to operate without interruption and the need for bigger or additional components.

Partial Reconfiguration also enables designers to manage power consumption by swapping out high-power consuming functions for more power-efficient functions when the highest performance is not required.

Xilinx made its fourth generation Partial Reconfiguration easier to use with a more intuitive design flow and interface. This includes an improved timing constraint and timing analysis flow, automatic insertion of proxy logic to bridge static and reconfigurable partitions, as well as full-design timing closure and simulation capabilities. ISE Design Suite 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for Partial Reconfiguration applications.

Continued clock-gating innovation for lowering BRAM power consumption
To help customers make their designs more power efficient, Xilinx enhanced its Intelligent Clock-Gating technology, which was made available through acquisition of PwrLite Inc. in summer 2009, to enable the lowering of BRAM dynamic power.

Through a unique set of algorithms, the ISE Design Suite can automatically neutralize unnecessary logic activity. This is a primary factor behind power dissipation, as it enables power optimizations that were not applied at the RTL level to be implemented downstream after synthesis, thereby reducing overall dynamic power consumption by as much as 30 percent.

Starting in ISE Design Suite 12.2, the intelligent clock-gating optimization will also reduce power for dedicated RAM blocks in either simple or dual-port mode. These blocks provide several enables: an array enable, a write enable and an output register clock enable. Most of these power savings will come from using the array enable. The ISE Design Suite is the only FPGA tool suite which offers fine grain clock gating optimizations integrated to the place and route algorithms.

Simulation support for embedded designs
ISE Simulator (ISim) is now available for the embedded design flow through the Xilinx Platform Studio (XPS) and Project Navigator tools, enabling embedded designers to take advantage of the mixed language (VHDL and Verilog) simulator integrated with the ISE Design Suite.

The new version of ISim has several new productivity-enhancing features, including automatic detection and listing of design memories for viewing and editing. This new Memory Editor enables designers to explore what-if scenarios using a graphical way to force a value or pattern on a signal without needing to recompile the design. ISE Design Suite 12 also makes it possible for designers to navigate to HDL source from the waveform viewer.

Start designing today
ISE Design Suite 12 is rolling out in phases with intelligent clock gating for Virtex-6 FPGA designs already shipping now with the 12.1 release on May 3, 2010, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release, and AXI4 IP support to follow in the 12.3 release. The ISE Design Suite 12 works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.

Additionally, ISE Design Suite 12 software features an average of 2X faster logic synthesis and 1.3X faster implementation run times for large designs than previous versions and an improved embedded design methodology.

ISE Design Suite 12.2 is immediately available for all ISE Editions and list priced starting at US$2,995 for the Logic Edition. Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site.

Altera's Stratix V FPGAs provide RLDRAM 3 memory support

SAN JOSE, USA: Altera Corp. announced that its Stratix V family of FPGAs is optimized to support Micron Technology's next-generation reduced-latency DRAM (RLDRAM 3 memory).

Stratix V FPGAs feature a new memory architecture that delivers the FPGA industry's highest system performance with low latency and high efficiency. Stratix V FPGAs provide networking equipment manufacturers with a memory interface solution capable of transferring voice, video and data across the Internet quickly and efficiently.

“Micron's next-generation RLDRAM 3 memory is designed specifically to meet the requirements of today's high-bandwidth networking applications and enable a faster, more efficient transfer of data over the network,” said Bruce Franklin, senior business development manager for Micron.

“Our long-standing relationship with Altera, combined with their commitment to providing high-performance FPGA solutions, is giving designers an effective pathway to more easily implement our leading reduced-latency memory.”

Stratix V FPGAs deliver a high-throughput memory interface to external memory devices such as RLDRAM 3. All of the critical circuits in the device's read/write path are hardened to simplify timing closure at very high frequencies. To complement Stratix V FPGAs, Altera offers memory controller cores and associated design software that automatically reduces design cycle time when working with external memories.

“Altera and Micron have worked together for years on advancing the system throughput of our bandwidth-constrained customer base by improving the latency and performance of the FPGA memory interface. This enables our customers to get to market quickly with highly differentiated solutions,” said Luanne Schirrmeister, senior director of component product marketing at Altera.

“The new innovations made to the Stratix V memory architecture enable us to deliver the most efficient memory interface targeting today’s highest performance networking applications.”

Actel announces new FlashPro4 programmer

MOUNTAIN VIEW, USA: Actel Corp. has announced FlashPro4, the newest hardware programmer supporting Actel's flash FPGAs: the IGLOO series and ProASIC 3 series (including RT ProASIC3), SmartFusion and Actel Fusion families.

FlashPro4 also supports FPGA embedded software program and debug managed by Actel's SoftConsole Integrated Design Environment (IDE) for embedded processors.

FlashPro4 offers high performance communication through the use of USB 2.0 and is high-speed compliant for full use of the 480 Mbps bandwidth. For IGLOO nano 1.2 V core FPGAs, 1.2 V programming is supported.

"FlashPro4 provides our flash FPGA customers with the latest hardware technology for performing both hardware design implementation and software program implementation for embedded processor designs," said Wendy Lockhart, senior manager, design solutions, Actel.

"In addition, it provides a common approach for facilitating FPGA debug for tools such as Synopsys Identify RTL debugger and Actel's on-chip debug, plus SoftConsole, Actel's embedded software IDE. It is also low enough in cost that our customers can include it with their end systems, so their customers and support personnel can readily perform in-system programming updates in the field."

Key features
* Provides programming for hardware design for all current Actel flash FPGAs and embedded software design and debug for embedded ARM Cortex-M3, Cortex-M1, 8051s, and future embedded processor designs.
* Common interface for hardware and software debug for Synopsys Identify, Actel on-chip debug, and Actel SoftConsole embedded software IDE
Low cost in-system programming (ISP) hardware for a single FPGA or chain of Actel flash FPGAs.
* Supports 1.2 V programming for Actel IGLOO nano 1.2 V core FPGAs.
* Replaces and is fully backward compatible with the previous FlashPro3 programmer.

Actel's FlashPro4 programmer is now available for $49. The part number is FLASHPRO4. The kit includes a USB cable, a ribbon cable with 10-pin JTAG connector, and a quickstart card. The FlashPro software is available for free, either standalone or as part of all Actel Libero Integrated Design Environment (IDE) versions.

Altair unveils TD-LTE reference design for wireless terminal manufacturers

HOD HASHARON, ISRAEL: Altair Semiconductor, the world's leading developer of ultra-low power, small footprint and high performance 4G LTE chipsets, has announced the commercial availability of a new TD-LTE terminal reference design for use in a range of products, including USB dongles, data cards, CPEs and handheld devices.

The reference design features Altair's field proven FourGee-3100/6200 chipset and a complete and interoperability-tested LTE software stack. Spectrum bands supported include India's recently auctioned TD-LTE band 40, China's band 38, and a variety of other bands which are being trialed and deployed in Japan, North America and Europe.

The reference design features a unified TDD/FDD architecture using a single chipset and a single software stack, enabling a small form factor and cost efficient integration for multimode devices.

"The demand for TD-LTE products, mainly in emerging markets such as India and China, is rapidly increasing, forcing carriers to develop cost-effective solutions for this growing segment," said Eran Eshed, Co-Founder and VP of Marketing and Business Development at Altair Semiconductor.

"Thanks to the maturity of Altair's FD-LTE solution which had sampled in September 2009, and the extensive testing it had undergone with most tier one infrastructure vendors, releasing a TD-LTE version was a logical next step for us."

TD-LTE, a 4G wireless standard which was designed to operate in unpaired spectrum, is emerging as the de-facto 4G standard for TDD spectrum globally. Since China Mobile's selection of TD-LTE as its 4G upgrade path, TD-LTE has received strong support from carriers such as Reliance Industries (RIL), Softbank Mobile and others in Europe and North America as well as from carriers such as Yota, which recently announced a strategic shift from WiMAX to LTE.

Recently, Altair announced a partnership with San Francisco-based IPWireless to develop a suite of multi-band LTE modem products that will support key frequency bands ideally suited to global LTE deployments. The companies will integrate Altair's
cutting-edge software-defined radio baseband processor into IPWireless' LTE devices.

The first consumer-friendly LTE USB modem device will support multiple frequency bands including the 800MHz digital dividend band, 1800 MHz and TD-LTE's 2.5 GHz. Subsequent devices will also support the entire US 700MHz and AWS frequency.

Exar releases PowerArchitect 3.0 for programming PowerXR programmable power products

FREMONT, USA: Exar Corp. has released PowerArchitect 3.0, the next generation design software for Exar's digital Programmable Power -- PowerXR family of five innovative power controllers.

This latest release represents the industry's easiest to use and most flexible solution for quickly creating custom power supplies. PowerArchitect 3.0 is available for immediate download from Exar's website.

"Speed and flexibility are critical for modern power supply design," said Tim Maloney, senior director, Digital Power Marketing. "PowerArchitect 3.0 adds many new features such as a Design Wizard to quickly create a power system based on a pre-existing design which will enable our customers to move faster than ever before from prototype to production."

PowerArchitect 3.0 overview
PowerXR is a family of programmable power supplies and represents a new methodology for creating complex power systems by reducing risk and speeding development time. PowerArchitect is an interactive design tool that enables designers to quickly architect, prototype and then move their designs into production.

Using PowerArchitect to configure complex capabilities such as sequencing, voltage and current levels, dynamic provisioning and telemetry, designers can quickly make power updates as system requirements change.

Furthermore, the tool allows the seasoned power design expert to access all the advanced features, while also providing an intuitive interface for those not as familiar with power theory.

TI's C6EZFlo DSP software development tool automatically generates flawless prototyping code using a graphical interface

DALLAS, USA: Allowing digital signal processing developers to effortlessly leverage the computational power of TI's digital signal processors (DSPs), Texas Instruments Inc. (TI) has introduced the C6EZFlo graphical software development tool.

The C6EZFlo tool simplifies and accelerates the development process by enabling developers to generate prototype software on TI DSPs without learning new programming languages or specific DSP architecture.

The C6EZFlo's unique graphical interface enables developers to utilize drag-and-drop functionality to create a signal flow block diagram. The blocks in the diagram represent anything from a peripheral input/output data transaction to a specialized DSP filter kernel. The tool generates heavily commented and cleanly structured C code based on the block diagram, which the developer can use in its raw form or modify to adjust the design.

Developers can leverage C6EZFlo with TI's C6000 DSP devices, such as C674x DSPs, as well as DSP-based DaVinci video processors, including DM643x and DM648, which enables quick and easy prototyping for various end applications, including industrial imaging, industrial monitoring, test and measurement, music effects and medical imaging applications.

Intel 32nm High-K Metal Gate (HKMG) recognized as most innovative logic process

OTTAWA, CANADA: UBM TechInsights has announced Intel Corp. as the winner of the Most Innovative Logic Process award in TechInsights' 9th Annual Insight Awards. Intel's 32nm process was utilized in the Clarkdale/Westmere processors analyzed by UBM TechInsights.

Carl Wintgens, Senior Process Analyst at UBM TechInsights showed in his EETimes article that Intel has continued to deliver their major process nodes at a schedule that adheres to Moore's Law despite the serious challenges in sub-sub-micron process technology. Competitors have also been able to conform to the law, so far, but it appears schedules are slipping and Intel's technology lead is increasing.

Wintgens commented, "We completed the analysis of a 2nd generation HKMG process from Intel without having yet seen a 1st generation process in production from anyone else."

Far from being a simple shrink, there are noticeable improvements in Intel's 32nm devices over the 45nm generation, including transistor drive current (with PMOS approaching NMOS capabilities), reduced leakage current, and higher speed/performance all traced to process technology changes.

Icera powers Bandrich 21Mbps HSPA+ USB modem

BRISTOL, UK: Icera Inc., the Mobile Broadband semiconductor company, has announced that its HSPA+ soft modem, supporting HSPA+ Release 7 features to deliver 21Mbps peak data rates and 5.76Mbps in the uplink, is powering BandRich’s Bandluxe USB stick, C330, C331, and C339, now available on multiple carrier networks globally.

The Bandluxe C330 series is a range of highly versatile USB modems providing various UMTS band combinations; the C330 worldwide tri-band 2100/850/1900 MHz, the C331 single band 2100 MHz, the C339 dual-band 2100/900 MHz and quad-band GSM/EDGE in addition to HSPA+ connectivity, all in a compact, lightweight design. They also feature an integrated microSD card for portable data storage.

Stan Boland, President & CEO of Icera Inc., said: "As we have seen with operator announcements in recent weeks, HSPA+ is gaining increasing traction with carriers looking to maximize the return from their investment in 3G networks, while increasing network capacity in response to the unprecedented demand for mobile data.

"Icera’s advantage is to offer 21Mbps HSPA+ as a software upgrade to our existing HSPA platform, using the same silicon, saving design time and cost, and enabling our customers to get products to market faster."

Dr. Wen-Yi Kuo, CEO of BandRich, commented: "We selected Icera’s Livanto chipset for our 21Mbps device because it combines outstanding user experience with unparalleled network efficiency due to its high performance soft modem technology.

"The product and the company’s innovative technology is allowing us, in turn, to successfully deliver enhanced mobile broadband performance to our operator customers who are increasingly differentiating themselves through the quality and consistency of their mobile broadband experience."

Synopsys' Design Compiler Graphical shortens design schedule at Oticon

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Oticon taped out the digital signal processor (DSP) chipset for their next-generation hearing-aid devices ahead of schedule using Synopsys' Design Compiler Graphical RTL Synthesis, a key component of the Galaxy Implementation Platform.

Engineers at Oticon, a world leader in the design, development and manufacture of hearing aids, needed to add new features to the next-generation DSP without increasing design area and while maintaining a very tight schedule. This was especially challenging due to the routing congestion caused by the added functionality, which could have led to multiple design iterations and a longer design schedule.

To alleviate this congestion, Oticon's RTL designers deployed the congestion optimizations in Design Compiler Graphical during RTL synthesis, resulting in an easy-to-route netlist and predictable design closure ahead of schedule.

"We strive to deliver innovative hearing-aids to our customers, and minimizing the size and power consumption of these devices is critical to our success," said Mogens Balsby, director of Silicon Engines at Oticon.

"As we enhanced the feature-set of our next-generation DSP, we saw severe routing congestion due to tight chip area requirements. By utilizing Design Compiler Graphical's congestion optimizations, we eliminated this routing congestion upfront without having to increase our chip area, and taped out successfully ahead of schedule."

Design Compiler Graphical extends DC Ultra topographical technology to predict routing congestion "hot spots" early in the design flow, providing designers with visualization of congested circuit regions and performing specialized synthesis optimizations to minimize congestion in these areas. This enables RTL designers to avoid wire-routing congestion problems that occur during detailed routing and eliminate costly design iterations.

Additionally, Design Compiler Graphical provides access to IC Compiler's design planning capabilities from within the synthesis environment, giving RTL designers the ability to explore and converge on an optimal floorplan faster. It also produces physical guidance to IC Compiler physical implementation, tightening timing and area correlation to 5 percent while speeding-up IC Compiler placement by 1.5X.

By enabling RTL designers to achieve an optimal floorplan efficiently and passing physical guidance to IC Compiler, Design Compiler Graphical can double the productivity of the entire synthesis and place-and-route flow.

"Shorter, more predictable design schedules help our customers bring competitive products to market faster," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Synopsys continues to deliver innovative RTL synthesis technologies, such as congestion optimization, floorplan exploration and physical guidance to IC Compiler, enabling companies like Oticon to meet their challenging design and time-to-market goals."

SiliconFile selects Berkeley Design Automation's AFS platform

SANTA CLARA, USA: Berkeley Design Automation Inc., provider of the Analog FastSPICE unified circuit verification platform (AFS Platform), announced that SiliconFile Technologies Inc., a leading fabless provider of CMOS image sensors, has selected the AFS Platform for complex-block verification of its image sensor ICs for mobile imaging applications.

"We spend a significant amount of effort on block-level verification of our CMOS image sensors," said Do Yeong Lee, Chief Technology Officer at SiliconFile. "After extensive evaluation, we selected the Analog FastSPICE Platform for complex-block verification of our image sensors because it delivered nanometer SPICE accurate results 5x-10x faster than traditional SPICE simulators."

The Analog FastSPICE Platform is the industry's only unified circuit verification platform for analog, mixed-signal, and RF design. It always delivers nanometer SPICE accurate results, while providing 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive device noise analysis.

The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. It includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis, and AFS RF Analysis.

"We are very pleased that SiliconFile Technologies, a leading developer of CMOS image sensor ICs for mobile, videoconferencing, and surveillance applications, has selected the Analog FastSPICE Platform," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "SiliconFile's selection validates, once again, that Berkeley Design Automation is an essential partner to leading edge companies in the mobile imaging revolution."

Intel milestone confirms light beams can replace electronic signals for future computers

SANTA CLARA, USA: Intel Corp. has announced an important advance in the quest to use light beams to replace the use of electrons to carry data in and around computers.

The company has developed a research prototype representing the world’s first silicon-based optical data connection with integrated lasers. The link can move data over longer distances and many times faster than today’s copper technology; up to 50 gigabits of data per second. This is the equivalent of an entire HD movie being transmitted each second.

Today, computer components are connected to each other using copper cables or traces on circuit boards. Due to the signal degradation that comes with using metals such as copper to transmit data, these cables have a limited maximum length. This limits the design of computers, forcing processors, memory and other components to be placed just inches from each other.

Today's research achievement is another step toward replacing these connections with extremely thin and light optical fibers that can transfer much more data over far longer distances, radically changing the way computers of the future are designed and altering the way the datacenter of tomorrow is architected.

Silicon photonics will have applications across the computing industry. For example, at these data rates one could imagine a wall-sized 3D display for home entertainment and videoconferencing with a resolution so high that the actors or family members appear to be in the room with you.

Tomorrow's datacenter or supercomputer may see components spread throughout a building or even an entire campus, communicating with each other at high speed, as opposed to being confined by heavy copper cables with limited capacity and reach.

This will allow datacenter users, such as a search engine company, cloud computing provider or financial datacenter, to increase performance, capabilities and save significant costs in space and energy, or help scientists build more powerful supercomputers to solve the world’s biggest problems.

Justin Rattner, Intel chief technology officer and director of Intel Labs, demonstrated the Silicon Photonics Link at the Integrated Photonics Research conference in Monterey, Calif.

The 50Gbps link is akin to a “concept vehicle” that allows Intel researchers to test new ideas and continue the company's quest to develop technologies that transmit data over optical fibers, using light beams from low cost and easy to make silicon, instead of costly and hard to make devices using exotic materials like gallium arsenide. While telecommunications and other applications already use lasers to transmit information, current technologies are too expensive and bulky to be used for PC applications.

"This achievement of the world’s first 50Gbps silicon photonics link with integrated hybrid silicon lasers marks a significant achievement in our long term vision of ‘siliconizing’ photonics and bringing high bandwidth, low cost optical communications in and around future PCs, servers, and consumer devices," Rattner said.

The 50Gbps Silicon Photonics Link prototype is the result of a multi-year silicon photonics research agenda, which included numerous “world firsts.” It is composed of a silicon transmitter and a receiver chip, each integrating all the necessary building blocks from previous Intel breakthroughs including the first Hybrid Silicon Laser co-developed with the University of California at Santa Barbara in 2006 as well as high-speed optical modulators and photodetectors announced in 2007.

The transmitter chip is composed of four such lasers, whose light beams each travel into an optical modulator that encodes data onto them at 12.5Gbps. The four beams are then combined and output to a single optical fiber for a total data rate of 50Gbps. At the other end of the link, the receiver chip separates the four optical beams and directs them into photo detectors, which convert data back into electrical signals.

Both chips are assembled using low-cost manufacturing techniques familiar to the semiconductor industry. Intel researchers are already working to increase the data rate by scaling the modulator speed as well as increase the number of lasers per chip, providing a path to future terabit/s optical links – rates fast enough to transfer a copy of the entire contents of a typical laptop in one second.

This research is separate from Intel's Light Peak technology, though both are components of Intel’s overall I/O strategy. Light Peak is an effort to bring a multi-protocol 10Gbps optical connection to Intel client platforms for nearer-term applications.

Silicon Photonics research aims to use silicon integration to bring dramatic cost reductions, reach tera-scale data rates, and bring optical communications to an even broader set of high-volume applications. This achievement brings Intel a significant step closer to that goal.

Tuesday, July 27, 2010

ITC issues notice of final determination in Rambus matter regarding NVIDIA products

LOS ALTOS, USA: Rambus Inc. announced that the International Trade Commission (ITC) issued its notice of final determination in the action brought by Rambus against NVIDIA Corp. and other Respondents. In its notice, the ITC has affirmed the findings of the Administrative Law Judge (ALJ), with certain modifications. The final determination, including such modifications, has yet to be released.

On November 6, 2008, Rambus filed a complaint with the ITC requesting an investigation pertaining to certain NVIDIA products. The complaint sought an exclusion order barring the importation, sale for importation, and sale after importation of products that infringe nine of Rambus' patents. The accused products include graphics processors, application processors, media and communications processors, and chip sets which incorporate infringing memory controllers.

The complaint named NVIDIA as a proposed Respondent, as well as companies whose products incorporate the accused NVIDIA products and are imported into the United States.

These respondents include: Asustek Computer Inc. and Asus Computer International, BFG Technologies, Biostar Microtech and Biostar Microtech International Corp., Diablotek Inc., EVGA Corp., G.B.T. Inc. and Giga-Byte Technology Co., Hewlett-Packard, MSI Computer Corp. and Micro-Star International Co., Palit Multimedia Inc. and Palit Microsystems Ltd., Pine Technology (Macao Commercial Offshore) Ltd., and Sparkle Computer Co. Four of the asserted patents were later withdrawn from the investigation.

An evidentiary hearing on the asserted patents was held before the ALJ on October 13-20, 2009. On January 22, 2010, the ALJ issued an initial determination finding two Rambus patents to be not valid. The ALJ further determined three Rambus (Barth) patents valid, enforceable and infringed by the Respondents.

Today, Rambus received notice of the ITC's intent to issue a Limited Exclusion Order barring the importation of Respondents’ infringing products into the United States, as well as Cease and Desist Orders barring identified Respondents from selling any infringing products that were previously imported into the United States. Under the Limited Exclusion Order, the infringing products may be imported and sold during a 60-day Presidential review period if Respondents post a bond. The Commission has specified that the bond amount is 2.65 percent of the entered value of the subject imports.

"The ITC’s decision is another demonstration of the value of our continued commitment to innovation," said Thomas Lavelle, senior vice president and general counsel at Rambus. "We are extremely pleased with the ITC’s decision to issue a Limited Exclusion Order, signaling the strength of our innovation efforts beyond the Farmwald-Horowitz patents of our founders. The value of our patented inventions has been recognized by our current licensees, and we will continue our efforts to license others."

Link_A_Media Devices shipping LDPC SoC in mainstream 2.5-inch HDD products

SANTA CLARA, USA: Link_A_Media Devices (LAMD), a leader in the development of semiconductor SoC solutions for the data storage market, announces its low-density parity check (LDPC)-based SOC device is currently shipping in mainstream 2.5-inch mobile hard disk drive (HDD) products.

The mobile 2.5-inch form factor is the fastest growing segment of the HDD market, used in laptop computers, gaming consoles, USB external drives, and other consumer devices where cost and power consumption requirements are paramount.

Today's HDD SOC data recovery architectures are mostly based on concatenated coding schemes which use Reed Solomon error correction codes, invented almost 50 years ago. Increasing the storage density of the HDD magnetic media reduces the quality of the data read by the head, due to increased noise. Today's architectures can no longer support HDD manufacturers’ requirements to double the storage capacity of their drives every 18 months.

The LAMD LDPC data recovery architecture can tolerate significantly more noise on the recording medium at the expense of increased complexity relative to Reed Solomon decoders. Now, by using LAMD’s LDPC-based SOC solutions, HDD vendors can continue to double the storage capacity of their drives every 18 months.

Deployed in 320 GB/disk HDD capacity products, both at 5400 rpm and 7200 rpm, LAMD’s current LDPC-based SOC device reduces the number of errors read from a disk from 1 in 100 to 1 in 100 Million bits of data, relative to the previously-used concatenated coding schemes. This enables more efficient utilization of the available disk surface to store more data and reduce the cost per gigabyte (GB) of storage.

"HDD areal density is growing at a rate of about 30 percent per year while storage capacity requirements are increasing by more than 40 percent per year," said John Rydning, IDC's research director for hard disk drives. "To keep pace with storage capacity growth, HDD vendors are compelled to squeeze more storage capacity out of the available areal density by employing novel technologies such as low density parity code now available in a new SoC from Link-A-Media, the first SoC supplier to enter the HDD market in more than 16 years."

"We are very pleased to help usher in this new era of LDPC data recovery technology in the mobile HDD segment. Achieving the right balance of performance, cost, and power consumption was critical for the commercial adoption of this very powerful and complex technology in the mobile HDD market," said Dr. Hemant Thapar, CEO, Link_A_Media Devices.

"We are currently extending our LDPC technology capability to other segments of the HDD storage market, enabling HDD manufacturers to achieve higher capacity points and lower their costs by increasing yields of head and media components."

Link_A_Media Devices' SOCs are manufactured by Renesas Electronics, a leading manufacturer and supplier of semiconductor products to the most demanding applications including automotive, PCs and mobile devices.

Analog Devices simplifies wireless infrastructure system design with mixed-signal, digital pre-distortion development platform using Xilinx FPGAs

NORWOOD, USA: Analog Devices Inc. has collaborated with industry leading programmable-logic vendor Xilinx Inc. to introduce a radio architecture development platform that helps multi-carrier cellular base station manufacturers reduce engineering resources and improve time to market.

ADI’s MS-DPD (mixed-signal, digital pre-distortion) development platform simplifies the wireless infrastructure design process by allowing OEMs to quickly assess and reprogram the radio to remove non-linearities from the transmit paths and enhance radio power efficiency.

ADI's MS-DPD platform incorporates a high-performance RF and mixed-signal transmit and observation receiver chain supporting 2G, 3G and emerging 4G wireless protocols. Xilinx’s Virtex-6 FPGA ML605 (field-programmable gate array) Evaluation Kit connects to the MS-DPD board through an industry-standard VITA-57 FMC connector. Using this system, the FPGA can be used to implement required radio algorithms leveraging the ADI signal chain available on the MS-DPD.

With the highest dynamic performance in its class, the multi-carrier MS-DPD development platform simplifies component selection and board layout to make it easier for designers of multi-carrier GSM and multi-standard SDR (software-defined radio) base stations to develop FPGA-based DPD algorithms.

FPGAs also provide the flexibility to optimize the solution that competing fixed-function ASICs (application-specific integrated circuits) cannot, while providing a highly integrated, low cost, low power and high reliability solution to present day base station needs.

"In collaborating with Analog Devices, we have been able to create a more modular approach to radio development, leveraging the new industry-standard FMC connectors," said Manuel Uhm, director, Wireless Communications Business, Xilinx.

"Customers are able to rapidly evaluate Xilinx’s crest factor reduction (CFR) and DPD algorithms in conjunction with ADI’s high-performance transmitter solutions, saving considerable engineering time. Furthermore, customers can leverage the Virtex-6 ML605 FPGA Evaluation Kit and MS-DPD to develop and evaluate their own IP."

Verayo unveils new unclonable RFID chip

SAN JOSE, USA: Verayo, a security and authentication solutions provider, today launched a new RFID IC – the Vera M1HW. The new chip complies with ISO/IEC 14443-A standard and uses Verayo’s patented Physical Unclonable Function (PUF) technology to enable tag-reader mutual authentication. It also features 512 bits of read-write memory for applications to store, add or edit user data.

The Vera M1HW broadens the scope of applications for Verayo’s PUF-based chips to a multitude of industries including contactless loyalty and payment cards, mass transit and event ticketing, consumer product anti-counterfeiting, and secure identification and access cards.

Similar to its predecessor, the M4H chip, the M1HW enables authentication at low a cost compared to alternatives, enabling security and authentication in applications where cost has been a primary inhibitor.

"The Vera M1HW was an obvious evolution and addition to our new family of unclonable RFID ICs," said Anant Agrawal, CEO of Verayo. "The mutual authentication and read-write memory in the new IC will extend the benefits of PUF technology to new applications where data stored on the chip has to be securely accessed and changed. We are dedicated to continuing innovation and bringing the benefits of PUF and RFID technology to an even greater range of markets and customers."

Verayo's PUF technology is a “silicon biometrics technology. PUF technology exploits the unavoidable, unpredictable and random variations in the IC fabrication process to uniquely characterize each chip. The variations cannot be controlled, modeled or replicated, effectively rendering each PUF-based IC physically unclonable and ultimately enhancing security and reducing counterfeiting concerns.

The Vera M1HW is available immediately. Verayo works with all leading RFID tag vendors to build tags for various applications. Its RFID ICs work with standard HF RFID readers.

D2, TrendChip create VoIP-enabled solution for xDSL IADs

SANTA BARBARA, USA & HSINCHU, TAIWAN: D2 Technologies, the market leader in embedded software platforms that power IP communications, and TrendChip Technologies, the leading xDSL chipset provider, announced the availability of D2's vPort Gateway (GW) embedded VoIP software on TrendChip’s TC3182 ADSL2+ processor.

The combined solution allows OEMs/ODMs to quickly deliver advanced ADSL2+ Integrated Access Devices (IADs) that offer high-performance ADSL2+ and 802.11n with optimized carrier-grade VoIP functionality.

"D2 Technologies’ vPort VoIP solution is highly optimized and field proven," said Bomin Wang, president of TrendChip. "vPort’s carrier grade real-time voice engine will allow our OEM and ODM customers to minimize risk and accelerate time-to-market for best-in-class xDSL VoIP IAD products based on the TrendChip TC3182."

For this series of IAD solutions, the TC3182 incorporates the powerful processing core, MIPS 34Kc, two Virtual Processing Elements (VPE) and a multi-threading system structure.

This delivers not only the excellent network performance of wired speed, but also maintains the high definition quality of voice signals even under high network traffic. These solutions also offer voice compression coding formats, such as G.711, G.726, G.729, and G.722, in order to satisfy the requirements of different telecommunications specifications.

"We are pleased to be collaborating with TrendChip to offer an industry leading VoIP-enabled xDSL platform to the market," said Doug Makishima, COO at D2 Technologies. "This solution offers carriers, OEMs and ODMs a way to deliver a single device that delivers ultra high speed Internet connectivity combined with high voice quality for premium voice/video/data services."

D2's vPort GW provides carrier-grade VoIP application, protocol and DSP features for wired/wireless CPEs such as ATA, gateway/router, IAD, and FMC products. vPort's advanced softDSP voice engine includes a comprehensive list of narrowband and wideband/HD CODECs, dynamic adaptive jitter buffer, packet loss compensation, VAD/CNG, DTMF tone generation/detection, echo cancellation, caller ID, FAX relay and more.

vPort delivers the best VoIP performance, quality and interoperability in the industry, and is highly optimized not just for quality, but for a small memory footprint and low CPU MHz impact. In fact, D2's VoIP software is the most widely deployed in the market today, powering more than 40 billion minutes of VoIP traffic each month across top-tier OEM deployments in consumer, enterprise and carrier environments worldwide.

FiberHome selects Celeno to support Shanghai Telecom with wireless HD IPTV

RA’ANANA, ISRAEL: Celeno Communications, a leading provider of semiconductors for multimedia Wi-Fi home networking applications, announced that FiberHome Telecommunication Technologies Co., Ltd has selected Celeno’s CL1800 high performance Wi-Fi system-on-a-chip (SoC) to enable its HG500 and HG230 optical network gateways with carrier-grade Wi-Fi for IPTV streaming. FiberHome is a leading telecommunications provider in China.

The collaboration between Celeno and FiberHome addresses the expansion of Fiber-to-the-Home (FTTH) network in China, and the growing demand for wireless HD IPTV home networking to support advancements in the digital home towards a full wireless life style. The solution, which is on display at the World Expo 2010, from May 1 – October 31 in Shanghai, China, will also be rolled out in the Shanghai Telecom’s metropolitan fiber network.

China Telecom launched a massive FTTH network to service triple-play services across the country. Shanghai Telecom, an operating unit of China Telecom, officially launched its program in June 2009, and other provinces are soon to follow. Shanghai Telecom selected FiberHome's The FiberHome optical gateway to target FTTH deployments, providing fast broadband access capability and triple-play services: data, voice and HD IPTV.

By leveraging Celeno's Wi-Fi chipset, the FiberHome optical gateway distributes IPTV wirelessly, providing cost-effective home network self-installation without the trouble of house wiring, enabling the flexibility to watch video content anywhere around the house.

Virage Logic expands semicon IP portfolio with silicon-proven SiANA analog IP offering

SOC SUMMIT; TAIPEI, TAIWAN: Virage Logic Corp. has announced the expansion of its broad semiconductor IP product portfolio with the introduction of SiANA, a new offering of silicon-proven analog IP components essential for building multimedia consumer electronics devices.

Comprising of clock sources, data converters, and sensor circuits, the product-proven, area efficient, high performance SiANA IP offering is designed for low power in TSMC’s 40, 65, and 90-nanometer (nm) process nodes. The portfolio provides the essential building blocks for general purpose System-on-Chip (SoC) implementations, as well as precision subsystems for multimedia and communications.

"With the new SiANA analog IP portfolio, Virage Logic can now provide the essential building blocks in a wide range of multimedia and communications analog systems," said Joshua Rom, vice president and general manager of Virage Logic’s Analog Solutions business unit.

"The offering includes analog IF interfaces suitable for 2.5G, 3G, GPS, DVB-T, DVB-H, S-DMB, WiFi, WiMAX, WHDi-1.5, WiBro, and other telephony and data communications, as well as CD quality audio and RGB, component, S-video, and composite video applications. Because these IP components were initially developed by Research and Development teams at NXP and Philips Electronics, the offering is product proven in a wide range of process nodes."

Rom concluded, "Because customization plays an essential role in the analog IP business, we provide integrated and hardened analog front-end blocks, delivering a single GDSII for audio, video or IF system solutions."

"We named Virage Logic as our early development partner on the 40nm process node in 2007 and worked closely with them to ensure early adopter customers had access to quality IP when we first introduced our 40nm process," said Shauh-Teh Juang, senior director of Design Infrastructure Marketing Division at TSMC. "The availability of a complete line of silicon proven 40nm analog IP underscores how our longstanding partnership with Virage Logic benefits our mutual customers."

"Virage Logic’s customers benefit from the convenience of working with a single broadline supplier of silicon-proven IP to help accelerate their SoC development. This now extends beyond the previous Virage Logic portfolio of memory-related IP to embrace analog functionality," said Rich Wawrzyniak, senior analyst for ASIC and SoC at Semico Research.

"From a design point of view, the ability to obtain more highly-differentiated IP from a single source can reduce the time spent in finding and qualifying other IP vendors for the other functions every SoC needs. This also extends to the needs of the design team for obtaining support functions from the IP vendor after the initial licensing phase is over. Obtaining more varied, high-performance IP from a single source increases the efficiency of SoC design teams because they can concentrate their time on doing designs instead of hunting for the right IP to fit their needs."

According to Semico Research, the analog IP market grew 7 percent in the fourth quarter of 2009, recovering from a negative growth in the first half of the year. Semico believes the analog IP market will show at least 15 percent growth for 2010 compared with the previous year and continue with strong positive growth through 2015.

The rise in the use of analog IP in complex SoC designs is attributable to the increasing need of these silicon solutions to move beyond purely digital functions and to interface more fully with the outside world, which is analog in nature. IP companies that have strong analog product portfolios are of increasing value to SoC design teams who must add more analog functionality to meet changing market requirements for their silicon solutions.

SanDisk launches smallest USB flash drive in North America

MILPITAS, USA: SanDisk Corp. has announced the availability of its smallest USB flash drive to US and Canadian consumers.

The SanDisk Cruzer Blade is about the size of a standard size paper clip and weighs approximately the same as a penny, creating a tiny footprint that fits easily on a keychain or mobile phone dongle. Despite its small size, the drive packs high-capacity storage at an affordable price.

Available in capacities ranging from 2 gigabytes (GB)1 to 16GB, the SanDisk Cruzer Blade lets consumers take their favorite digital content with them wherever they go. A 4GB drive can store 1,000 songs, 1,200 high-resolution photos, or 8 hours of 768kb/s video*. The SanDisk Cruzer Blade offers reliable storage in a sturdy form factor, helping consumers rest assured that their digital content is safe.

"At half the size of some other USB drives, our compact Cruzer Blade provides consumers with highly portable storage at a great value," said Kent Perry, director, retail product marketing, SanDisk. "The drive lets users transfer their digital data quickly between computers, and delivers a storage boost to devices such as netbooks that often need additional memory but are difficult to upgrade easily."

The SanDisk Cruzer Blade USB flash drive is available now in the United States and Canada at, with prices ranging from $14.99 to $77.99. The drive carries a two year limited warranty.

Freescale, Indesit ally on smart appliance solutions for ZigBee connected white goods

AUSTIN, USA: Freescale Semiconductor and Indesit Company recently demonstrated their ability to help their customers create 'smart' products by showcasing a Smart Washer that can regulate its own energy use based on cost and availability at the Freescale Technology Forum in Orlando.

The Indesit Company's Smart Washer, equipped with a Freescale ZigBee node, is able to adjust its cycle starting time according to energy cost (in a variable costs environment) and green power availability, getting this information from the local utility via a ZigBee enabled Internet connection to the Smart Grid. The Indesit Company is a leading European manufacturer and distributor of major domestic appliances.

The Freescale-Indesit collaboration is further evidence of the Smart Grid focus of both companies. Freescale's ZigBee technology helps designers to reduce design complexity, lower bill of material costs and deliver high performance solutions to help appliance customers build ZigBee connected smart houses.

"Working closely with Indesit -- a leading producer of industrial white goods -- underscores Freescale’s leadership in a broad array of wireless communications targeting the smart grid and energy efficiency," said Brett Black, Wireless Connectivity manager at Freescale.

"We are pleased to team up with Freescale on our products using their technology," said Stefano Frattesi, Indesit Company’s Innovation for Design manager. “The Smart Washer confirms our commitment to innovation for the benefit of the environment and demonstrates our pioneering research in the field of Smart Grid to help reduce energy consumption and provide our customers increasingly innovative solutions."

Freescale was one of the first companies to join the ZigBee Alliance and provides platform solutions supporting ZigBee Smart Energy, RF4CE, Healthcare and Home Automation. Freescale continues to invest in energy efficient technology for the Smart Grid, allowing its customers to address the increasing demand of energy smart control.

Indesit recently launched two projects focused on leveraging the Smart Grid to make its products more energy efficient. The first is a global program for domestic trials of intelligent refrigerators with Indesit’s Dynamic Demand Control technology, which is capable of managing consumption on the basis of grid availability. The second is Energy@home, a research project that will experiment with a system of home appliance interconnections designed to optimize energy consumption.

Virage Logic continues to broaden semicon IP offering with new portfolio of SoC infrastructure solutions

SOC SUMMIT, TAIPEI, TAIWAN: Virage Logic Corp. has announced the further broadening of its already extensive System-on-Chip (SoC) infrastructure IP portfolio with its new Integra product line.

Based on the proven technology that Virage Logic acquired from NXP in November 2009, the Integra portfolio of SoC Infrastructure IP includes advanced Multi-layer and Control networks, embedded Quality of Service (QoS) functionality as well as memory controllers for embedded SRAMs/ROMs.

This complete solution is able to provide the central back-bone of any SoC and extends Virage Logic’s ability to serve as a single source provider of highly differentiated, production proven IP.

"The Integra SoC Infrastructure IP portfolio was designed to be high performance and cost effective, and therefore is ideally suited for any application in today’s world of internet-enabled programmable multi-core devices," said Henk Hamoen, director of marketing for SoC Infrastructure at Virage Logic.

"Integra addresses the global drive for energy conservation by applying a power islands methodology; a technology that at the same time improves time-to-market because its implementation is extremely physical design friendly. Production proven innovative data and control interconnect networks as well as memory controllers for embedded SRAMs/ROMs are provided. The QoS Engine also provides unique system Quality of Service features that enable perfect media streaming in complex multi-media SoCs including Digital TV, Set Top Boxes and portable audio/video devices."

The Integra Multi-Layer and Control Networks connect with Virage Logic's ARC processor family via industry standard AMBA interfaces and provide an easy hook-up to the recently introduced portfolio of Processor Peripherals. The Integra QoS Engine also easily interfaces to the company's Intelli DDR controllers, while the Integra Memory Controllers are optimized for use with Virage Logic's SiWare Memory embedded SRAM/ROM memories.

In addition, because the Integra product portfolio ideally fits the needs of market segments where Virage Logic is already a leading supplier, including Automotive, Microprocessors, Digital TV, Set Top Box and Multi-Media devices, customers benefit from the convenience of being able to rely on a single trusted IP provider for complete IP subsystems.

TowerJazz's CMOS sensor process powers Cypress' new global shutter image sensor

MIGDAL HAEMEK, ISRAEL & SAN JOSE, USA: TowerJazz and Cypress Semiconductor Corp. announced that TowerJazz’s 0.18-micron CMOS image sensor (CIS) process is being used to power Cypress’ new 25-megapixel industrial high-sensitivity, high-speed CMOS image sensor targeted for the high-end machine vision market.

The VITA 25K sensor, sampling now, provides the market’s highest throughput for a device with a unique pipelined and triggered global shutter architecture. According to a report by Roy Szweda, RNR Associates, the forecast for image sensors used in the industrial market is likely to reach close to $840 million by 2014.

The VITA 25K sensor has 32 10-bit digital Low Voltage Differential Signaling (LVDS) outputs that enable transfer of image data over a standard industry protocol at low power and low noise.

Each channel runs at a 620 Mbps, which results in a high frame rate of 53 frames-per-second (fps) at full resolution for undistorted images and fast readout. Manufactured using TowerJazz’s CIS process, the sensor is ideal for high-end machine vision applications, such as inspection machines; biometric inspection, such as next-generation palm print readers; and intelligent traffic systems.

"This product joins a series of successful projects we have collaborated on with TowerJazz using their leading CIS process technology," said Georges Hiltrop, General Manager, Image Sensor Business Unit, Cypress. "We are able to continue bringing to market faster and higher sensitivity CMOS image sensors due to our design expertise and patented IP in custom image sensors combined with TowerJazz’s high performance CIS process capabilities."

"TowerJazz and Cypress have collaborated on CIS projects for more than 10 years, enabling a wide portfolio of products for industrial imaging, high-end cameras, barcode, medical and dental imaging," said Dr. Avi Strum, Vice President and General Manager, Specialty Group, TowerJazz. "The long cooperation between our teams is becoming stronger as we continue to align on innovative and market changing projects and products with a clear advantage in the market."

Samples of the VITA 25K image sensor are currently available, with production devices expected in the first half of 2011.

Virage Logic's ARC Sound AS221BD dual-core processor targets Blu-ray audio

SOC SUMMIT, TAIPEI, TAIWAN: Virage Logic Corp. has announced the new ARC Sound AS221BD dual-core processor for High Definition (HD) Audio System-on-Chips (SoCs) targeting Blu-ray Disc 7.1 channel 192kHz/24-bit output HD Audio processing applications.

This new product extends Virage Logic’s Sound-to-Silicon solution into HD and also includes a complete software stack with all required codecs, media streaming framework, and Blu-ray Disc use cases. The AS221BD dual-core processor, with all memories to run the full Blu-ray software stack, occupies 0.81mm2 in a 65-nanometer (nm) low power (LP) process which is as small as half the size of other alternatives.

The processor is one and a half to three times more power efficient than existing solutions. The high performance AS221BD delivers 3.5 GOPS at 350MHz. Combining both hardware and software, the HD Sound-to-Silicon solution is easy to integrate, significantly reducing time-to-market and development costs for users compared to partial licensing or fully developing solutions in-house.

"The dual-core AS221BD targeting Blu-ray Disc and HD Audio SoCs is an exciting new ARC processor offering from Virage Logic," said Dr. Yankin Tanurhan, vice president and general manager, Processor, SoC Infrastructure, Application Specific IP (ASIP) and NVM Solutions business units at Virage Logic.

"Blu-ray Discs and HD television broadcast are bringing HD Audio content to the consumer, and a whole new range of audio SoCs need to be built to support it. Virage Logic’s fully-integrated solution enables SoC designers to bring HD Audio to next-generation chips addressing the STB, DTV, Blu-ray players/recorders, networked media servers, networked attached storage and wired/wireless audio transmission markets. We are particularly proud of the AS221BD as it is the first core developed by Virage Logic since the ARC acquisition in November 2009."

Velammal Engineering College inaugurates 'Virtual Instrumentation Centre' under Planet NI Initiative

CHENNAI, INDIA: National Instruments has established a Centre of Excellence (CoE) in partnership with Velammal Engineering College, Chennai for innovation and creativity in the field of Virtual Instrumentation.

This CoE is the first of its kind in the state with a view to improve the quality of engineering education in India and spread the concept of Virtual Instrumentation. The partnership is a part of the initiatives taken by Planet NI (Nurturing Innovation) foundation.

The CoE will introduce latest industrial standard technologies and develop products which can encourage ideation and innovation in the areas of embedded technology among engineering students and technical professionals of the country.

The CoE will work on research areas like embedded Industrial Control, Image Processing, Robotic System Design, Measurement & Automation, Wireless Sensor network by encouraging ideation and innovation through projects based on real world applications, access to industry events, educational workshops, and training sessions on NI LabVIEW.

While inaugurating the CoE with M.V. Muthuramalingam, Chairman, Velammal Educational Trust, Jayaram Pillai, managing director India, Russia & Arabia, National Instruments said: “The establishment of the CoE will strengthen our engagement with the academia in the country. This association will help us equip students with the skills required to undertake research and development in the changing technology environment. With this initiative we will be able to contribute to the development of the limited exploratory or research-based education.”

“With acknowledgement of research intensive needs on the part of industry, meeting these needs for the future engineers is an essential part of bridging the academia-industry gap present,” he added.

Virtual instruments provide significant advantages in every stage of the engineering process, from research and design to manufacturing test. Virtual Instrumentation aids all stages of the engineering process, from research and design to manufacturing test.

With this initiative the centre will offer candidates an opportunity to work to the highest academic standards and will seek to bridge the gap between the industry & the academia by creating an experiential learning environment for engineering students in the state as well as across India.

Planet NI and Velammal Engineering College is committed towards developing quality engineers who can take the country forward with continuous innovations in technology.

EDA Tech Forum worldwide event series opens registration for two conferences in India

BANGALORE, INDIA: The EDA Tech Forum worldwide event series, a key technical and networking resource for the electronics engineering community, has announced the opening of registration for events in Bangalore and New Delhi, India.

These one-day conferences will deliver a wealth of technical information to help electronics engineers tackle today’s toughest design challenges.

The first event takes place August 18 at the Hotel Taj Residency in Bangalore, followed by the second on August 20 at the Hotel Radisson MBD Noida in New Delhi.

Along with technical breakout sessions, three keynote speakers will provide their insights into the latest developments and trends in the EDA industry:

• Pravin Madhani, General Manager, Place and Route Division, Mentor Graphics will present “100 Billion Transistor Chip”
• Pamela Kumar, Director, India STG Engineering Labs, IBM, will discuss “Microelectronics for a Smarter Planet”
• Manjunath Hebbar, Vice President and Head - Strategic Services, HCL Technologies Ltd. will present “Social Product Innovation and Electronic Design Industry”

The EDA Tech Forum series brings together over 7,500 attendees annually from over 2,000 companies. It provides an excellent opportunity for designers and engineers to network with their peers and, conversely, for EDA solution providers to reach those markets.

Event activities include keynotes discussing the latest EDA issues, a vendor fair with new product demonstrations, and technical breakout sessions in four tracks:

• Maximizing Front-end Design: From ESL through RTL;
• Accelerate Time to Manufacturing;
• Embedded Symposium: Innovations in Embedded Software and User Interface Development; and
• Increase Productivity in System-level Design.

In addition to the worldwide series of events, the EDA Tech Forum series also offers the EDA Tech Forum quarterly technical journal, available as a printed or online publication. The magazine provides a forum in which to discuss, debate, and communicate the electronic industry's most pressing issues, challenges, methodologies, problem-solving techniques, and trends.

Sponsors of the EDA Tech Forum series include Altera, ARM, Mentor Graphics, and GlobalFoundries.

MIPS delivers reference implementation for Skype on MIPS-based devices

SUNNYVALE, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced that support for the MIPS architecture is included in new SkypeKit developer tools available now from Skype.

Through the SkypeKit closed beta program, MIPS Technologies has developed a Skype reference implementation for the MIPS architecture—the leading architecture for the digital home.

Skype is software used by individuals and businesses to make video and voice calls, send instant messages and share files with other Skype users. Developers now have the ability to build Skype functionality into MIPS-Based™ devices such as DTVs, set-top boxes and digital media adaptors.

Art Swift, vice president of marketing, MIPS Technologies, said: "We are pleased to offer our licensees yet another key piece of the picture for next-generation connected devices. By participating in the SkypeKit beta program, our licensees and their customers can now develop Skype solutions to enable Skype users around the globe to communicate through a range of MIPS-Based products.

"The MIPS architecture offers compelling performance and power consumption advantages. These advantages, together with the work we are doing with platforms such as Skype, Android, Adobe Flash Player 10.1, Yahoo! TV Widgets and others, are enabling our customers to quickly and easily create the next generation of innovative SoCs."

Infineon intros 30V MOSFETs

NEUBIBERG, GERMANY: Infineon Technologies AG has introduced a 30V Power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the world’s lowest R DS(on) for high current automotive applications.

The new OptiMOS-T2 30V MOSFET is a N-channel device with drain current of 180A and R DS(on) of just 0.9mΩ at 10V gate-to-source voltage. The IPB180N03S4L-H0, which comes in a D2PAK-7 package, addresses customer needs for Power MOSFETs in standard packages offering both high nominal currents and lowest R DS(on) at lowest cost.

Based on the second generation of Infineon’s powerful trench technology for power MOSFETs, the OptiMOS-T2 device is ideal for high-current automotive motor drive applications, electric power steering (EPS) and especially start/stop functionality.

For cost and efficiency reasons there is a clear industry trend towards trench concepts. Power MOSFET trench technologies, such as OptiMOS-T2, exhibit significant improvement in both R DS(on) and gate charge compared to previous technology. This results in a Figure of Merit (FoM), which is the product of gate charge and R DS(on), that is among the industry’s lowest.

In addition, the innovative high-current “Powerbond” technology from Infineon addresses the wirebond limitations in a MOSFET, reducing the R DS(on) drop of the wirebond and increasing the current capability. This also enhances reliability by keeping the wirebonds cooler. The latest Powerbond technology enables up to four double-stitch 500µm wirebonds in a single MOSFET which permits 180A current rating in a standard package.

OptiMOS-T2 technologies and the robust packages are designed to sustain 260 °C during reflow soldering at MSL1 (Moisture Level 1) and have lead-free plating for RoHS compliance. The IPB180N03S4L-H0 power MOSFET is fully qualified according to the specifications of Automotive Electronics Council (AEC-Q101).

Infineon’s advanced trench technology provides low gate charge, low capacitance, low switching losses and excellent FoM to deliver a new peak in electrical motor efficiency while minimizing EMC emissions. In addition, optimized gate charge enables smaller driver output stages.

The IPB180N03S4L-H0 addresses high-current applications (over 500A) where the operation of many MOSFETs in parallel is required. As the IPB180N03S4L-H0 provides 180A nominal current it allows the reduction of the required number of parallel MOSFETs by one for high current systems to optimize current sharing, thermal behavior and costs. As automotive electric motors move to Pulse Width Modulation (PWM) control to increase efficiency, OptiMOS-T2 30V products can also provide battery protection through reverse connection.

“Infineon provides a broad portfolio of best-in-class automotive MOSFETs based on its OptiMOS-T2 trench technology offering superior performance and excellent quality in robust packages,” said Dr. Torsten Blanke, Product Marketing Director, Standard Automotive Power at Infineon Technologies. “Introducing the new 30V OptiMOS-T2 device with 180A nominal current Infineon again sets the benchmark for highest current capabilities in standard packages and lowest R DS(on) in trench technologies.”

The 30V IPB180N03S4L-H0 device with 180A drain current and a R DS(on) of only 0.9mΩ is released for volume production. In addition, Infineon offers a variant with 30V/180A (IPB180N03S4L-01) providing a R DS(on) of 1.05mΩ at 10V gate-to-source voltage for very cost critical applications. Both high-power MOSFETs are available in standard D 2PAK-7 package.

Third annual SoCIP show a major success

SHANGHAI, CHINA: The annual SoC IP Symposium is China’s premier show to feature the latest technology and product information for the SoC design community.

This year’s show, which was held in Shanghai and Beijing in June, attracted over 300 qualified attendees and 14 exhibitors. The show is organized by S2C, a leading rapid SoC prototyping company, headquartered in San Jose, CA with development and support centers in Shanghai and Beijing.

This one day show allows for attendee interaction with the IP and design service vendors in both question and answer sessions and vendor-attendee interaction at the exhibit portion of the show. Attendees have the opportunity to share their design specifications and challenges and explore solutions with the vendors. S2C, as the organizer, thanks all the exhibitors, and media for their participation in making SoCIP2010 a valuable resource for the SoC design community.

The SoCIP show is an important platform for SoC design community. The key reason is the history of the industry. After years of development of the semiconductor industry, the market has segmented into increasingly fine division of services and silicon IP, from the earliest IDM to the broad spectrum of IC design and design service companies, IP providers, and semiconductor foundries. The SoC designer is faced with an ever increasing array of potential solutions to their design problems.

SoCIP success is largely due to a rapidly growing Chinese SoC industry. As the organizer of the show, S2C not only understands the IP needs of the industry but is familiar with the best in class foreign suppliers to help customers select the best solutions in China to meet their SoC and IP design solutions.

In China, the chip design industry and government support are inseparable. In 2008, in the face of the global economic crisis, the Chinese Government made a series of initiatives to strongly support a variety of IC projects, which brought a large demand for silicon IP.

The National Software and Integrated Circuit Public Service Platform (CSIP) Deputy Director Qiu Shanqin was invited to participate in SoCIP 2010 and gave the keynote speech "Build SoC Reference Platforms to Promote the Use of Silicon IP in different Applications." This demonstrates the Government's active support of the silicon IP industry in China.

The show theme "The Era of Designing with System Prototyping IP” highlights that SoC design methodologies shows a new trend that is a common FPGA prototype platform that facilitates IP development, demonstration, evaluation, integration even SoC verification. This design methodology has been widely recognized by exhibitors and visitors.

In SoCIP 2010, there were a number of IP vendors using S2C’s TAI Logic Module to as a prototype design and verification platform utilizing Prototype Ready IP, such as CAST, Northwest, Innosilicon, etc. This platform enables SoC designers to facilitate IP evaluation and verification throughout the design saving up to 6 months of project development time.

Exhibitors voiced overwhelmingly positive responses to the show. Renesas MCU Products Electronic Marketing Manager Zhou Shao Xiang said: "This is our first time SoCIP seminar exhibition, we are pleased to see so many industry participants, it is indeed a good opportunity for our customers to visit face to face."

Another Cosmic's Analog IP director Sundararajan Krishnan said: "A great organization. It was all related customers, great, I hope next year to invite more customers." Mao from Beijing Vimicro said, "SoCIP2010 show was well prepared to the vendor presentations had good effects."

SanDisk announces planned retirement of Dr. Eli Harari; Sanjay Mehrorta named as CEO, Michael Marks as chairman

MILPITAS, USA: SanDisk Corp. announced that after 22 years of dedicated service to SanDisk, Dr. Eli Harari, founder, chairman and CEO, will retire from his current positions on December 31, 2010. Dr. Harari will provide advisory services, particularly technology related, to the Company for a period of two years starting January 1, 2011.

As part of the succession planning process, the Board of Directors of SanDisk is pleased to announce that it has appointed Sanjay Mehrotra, currently SanDisk's president and COO, to be the president and CEO of the company, effective January 1, 2011 and has appointed him to the company's Board of Directors effective July 21, 2010.

The Board is also pleased to announce that Michael Marks, a member of the SanDisk Board since 2003, will assume the role of chairman effective January 1, 2011. Marks is president of Riverwood Capital, LLC, a private equity firm, and formerly was CEO of Flextronics for 12 years.

"Over the past 22 years, SanDisk has grown to become a leading provider of flash memory-based storage solutions with total annual revenues approaching $5 billion," said Dr. Eli Harari. "I have been fortunate to lead this great company and its people all these years. The company's management is broad and deep, and I am very pleased to hand over my responsibilities to Sanjay Mehrotra, my co-founder and business partner, at the end of this year. Our business and technology leadership have never been stronger and I'm confident the company will scale new heights under Sanjay's leadership."

Irwin Federman, lead independent director, SanDisk, said: "Eli is a true visionary, and he has been instrumental in the creation of the flash memory industry through both his technology leadership and through his seeding and development of multiple large end markets.

Eli has demonstrated remarkable versatility in his ability to grow from entrepreneur to a highly regarded CEO of a multi-billion dollar global corporation. As an immigrant to America, he is a true American success story. On behalf of the employees of SanDisk and the Board of Directors, it is my privilege to have served along with Eli and I thank him for all his hard work in creating a well respected and dynamic technology company."

Federman continued: "After careful consideration, the Board of Directors is pleased to appoint Sanjay Mehrotra as SanDisk's President and Chief Executive Officer, effective January 1, 2011. Sanjay is a strong and dynamic leader. He has worked very closely with Eli since SanDisk's inception, and there is no person better qualified to take the baton and lead SanDisk through the next phase of its evolution."

"It has been an honor to work with Eli over the years, and the company's success is a testimony to Eli's vision and leadership," said Sanjay Mehrotra, president and COO.

"I would like to thank Eli and the Board of Directors for their confidence in entrusting the leadership of SanDisk to me. I look forward to further building on our impressive tradition of delivering innovative flash memory solutions to the industry. As always, I'm committed to creating value for our customers, our employees and our shareholders."

Freescale to host sixth annual Technology Forum in India

INDIA: Freescale Semiconductor will host its annual Freescale Technology Forum (FTF) India at Hotel Leela Palace, Bengaluru, on August 18-19, 2010. The theme for this year’s FTF will be POWERING INNOVATION.

Freescale Senior Vice President, Chief Sales and Marketing Officer, Henri Richard will present the opening keynote address at FTF India. K. Jairaj, Chairman to Karnataka Renewable Energy Development Limited (KREDL) and Additional Chief Secretary to Government of Karnataka will be the guest keynote speaker at the forum.

The closing session of FTF will feature a panel discussion on ‘Smart City and Smart Grid – Opportunity and Challenges’. The closing panel discussion scheduled for Thursday, August 19, 2010 will feature eminent technologists from Distribution Utility, Metering and Technology companies.

"Innovation is the solitary remedy to overcome the economic hindrances that are almost inescapable in today’s delicate market situation. Innovative products and technology can help cut costs, increase efficiency, empower the people and can even uplift the rural infrastructure like in case of smart grids in the power sector” said Ganesh Guruswamy, Vice President and Country Manager, Freescale Semiconductor India Pvt Ltd.

“One of the primary motives of FTF is to focus on providing developers with insights into future embedded technologies. This year’s forum will catalyze innovation and promote it by showcasing revolutionary technologies that would transform our lives. We will also provide a comprehensive, market-focused spectrum of enablement solutions and ecosystem partnerships which are needed to help developers innovate and accelerate their time to market,” added Guruswamy.

FTF India 2010 will include more than 71 hours of technical training sessions organized into tracks focusing on Automotive, Consumer, Industrial, Networking and Enabling Technologies. The event will also feature about 50 demonstrations on new technologies from Freescale and its partners.

“FTF is our biggest customer event and a platform to showcase new technologies that have the potential to change the world. The forum, which is in its sixth year, has attained iconic status in the semiconductor industry. The event of such stature will only add to the exuberant and stimulating environment that we have for innovation and partnership in India” said Vivek Tyagi, Country Sales Manager, Freescale Semiconductor India.

NetLogic announces breakthrough multi-core processor solution that integrates 128 nxCPUs

SANTA CLARA, USA: NetLogic Microsystems Inc. has announced the innovative XLP8128S multi-core communications processor solution.

It integrates 128 nxCPUs and over 160 programmable processing engines to deliver an unprecedented 160Gbps throughput and 240 million packets-per-second (Mpps) of intelligent application performance for next-generation 3G/4G mobile wireless infrastructure, enterprise, storage, security, metro Ethernet, edge and core infrastructure network applications.

The new XLP8128S multi-core processor solution integrates the breakthrough XLP processor architecture to offer unparalleled processing performance with scalability to 128 nxCPUs, each operating at up to 2.0 GHz and based on a best-in-class superscalar engine and out-of-order execution capabilities for converged data plane and control plane processing.

The 128 nxCPUs offer full cache and memory coherency over the high-speed Inter-chip Coherency Interface (ICI), enabling software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes.

The unique combination of superior processor cores and scalability from 1 to 128 nxCPUs deliver over 240 Mpps of intelligent application processing performance, making it the industry’s highest performance multi-core communications processors for intelligent Layers 4-7 network, services and application processing.

“NetLogic Microsystems is raising the bar with its third-generation multi-core processor by enabling an impressive 128 nxCPUs over the ICI interface while maintaining full cache and memory coherency. No competing product even approaches this level of performance,” said Linley Gwennap, principal analyst at The Linley Group. “The XLP processor offers numerous architectural advantages that enhance performance, scalability, and power efficiency.”

“Our ability to scale to 128 nxCPUs with full cache and memory coherency to deliver 160Gbps throughput and over 240Mpps of application performance is unprecedented in the industry, and enables a new class of equipment for our customers,” said Behrooz Abdi, executive VP and GM at NetLogic Microsystems.

“We are excited to continue to be at the forefront of technology innovation in the area of multi-core processing for next-generation network and communications infrastructure, security and storage applications.”

Monday, July 26, 2010

ST, Digi-Key encourage engineering with launch of design contest for students

GENEVA, SWITZERLAND & THIEF RIVER FALLS, USA: Electronic components distributor Digi-Key Corporation and STMicroelectronics have announced an exciting design contest for engineering students based on ST's iNEMO multi-sensor inertial measurement unit (IMU).

The aim of the contest is to show engineering students how easy sensors are to work with and help them learn how sensors can enhance their projects, improving both usefulness and usability. Designs can address applications such as man/machine interfaces, robotics, navigation, gaming and sports, remote monitoring (of industrial equipment or medical patients), and more.

ST's iNEMO is a unique evaluation and development tool that offers 3-axis sensing of linear, angular, and magnetic motion, as well as temperature and barometer/altimeter readings along with a 32-bit microcontroller and dedicated software – all on a single, small development board. iNEMO is in stock and available for purchase on Digi-Key's US and Canadian websites.

Each project must contain an iNEMO IMU and will be judged on the number of degrees of freedom (DoF) used, the quality of its hardware and firmware/software, the design's novelty, its use of daughter boards, and the project's ease of use and appeal of its user interface.

The grand-prize winner will receive a $5,000 cash prize along with an all-expense-paid trip, including airfare and accommodations for three nights, to Europe to visit the ST Development Labs in Catania, Sicily, Italy. Cash prizes of $2,500 and $1,000 will also be awarded to entrants selected as the second- and third-place winners.

Contest entrants must be currently-enrolled students, at least 18 years of age, who are residents of North American locations that do not prohibit, tax, or restrict such contests.

Qualified entrants must register to participate by October 30, 2010 and will need to purchase an iNEMO development kit, containing an iNEMO eval board, a complete, professional software development toolset and appropriate cables and software for $369 (value $4500). Completed submissions will be accepted until April 30, 2011 with winners notified by early July, 2011.

VXi chooses Conexant's embedded audio solution for USB headset adapter

NEWPORT BEACH, USA: Conexant Systems Inc. announced that its award-winning CX20562 speakers-on-a-chip audio solution was selected by VXi Corporation, a leading provider of best-in-class headset solutions, for a new USB headset adapter.

VXi’s X200 adapter is targeted at computer-based voice communications applications that require high-quality voice and audio including Unified Communications (UC), VoIP telephony, and speech recognition. The adapter is available now from VXi’s global network of distributors and resellers.

“VXi is well-known for developing high-quality telecommunications and speech recognition solutions, and we are pleased they chose our innovative audio solutions for their new X200 USB headset adapter,” said Phil Pompa, senior vice president of product marketing for Conexant. “We will continue to apply our extensive expertise in digital signal processing algorithms to further improve sound clarity in audio and voice applications.”

VXi’s new X200 USB adapter features Conexant’s proprietary noise-reduction and wideband acoustic echo-cancellation technologies, which dramatically improve voice and audio quality.

“Clear, natural sounding conversations are critical for businesses using IP-based voice communications to improve productivity and the end-user audio experience,” said Michael Ferguson, president and CEO for VXi. “Conexant’s advanced audio solutions deliver the performance required for these applications, which is why we chose their innovative technology for our new X200 USB adapter.”

IDT intros industry’s most flexible intelligent system power management IC

SAN JOSE, USA: Integrated Device Technology Inc. (IDT) has announced a highly integrated microcontroller-based Intelligent System Power Management Solution targeted for portable consumer products, such as Smartphones, portable navigation devices, mobile Internet devices and eBooks.

The unique architecture of the IDT P95020 features a best-in-class high-fidelity audio subsystem, clock generation, resistive touch controller, backlight LED driver, Li+/Polymer battery charger, multi-channel DC-to-DC converters and a high resolution analog-to-digital converter (ADC).

By embedding a microcontroller, the IDT P95020 offers full programmability and flexibility into designs using leading multimedia application processors. All of the functional blocks can be accessed via I2C. The programmable regulators satisfy the dynamic voltage adjustment required by application processors.

“The IDT P95020’s innovative architecture, with an embedded CPU, can manage all on-chip resources and also offload general housekeeping and I/O processing tasks from the application processor. This unique feature, along with programmable system power regulation blocks and an on-chip power management scheme, results in higher system performance and longer battery life,” said Farshad Zarghami, senior director of product marketing at IDT.

“Building around the IDT digital heritage combined with leadership in high-performance silicon timing, PC audio codec excellence and integration of newly developed high-performance mixed-signal mega blocks, the IDT P95020 is the first in a series of next-generation Intelligent System Power Management solutions being developed by IDT as part of its mixed-signal SoC growth strategy.”

The IDT P95020 is the latest generation of cost-effective, customizable Power Management Integrated Circuits (PMIC) that provide optimum performance, functionality, programmability and flexibility to the system designer of portable consumer applications.

Its subsystems consist of multiple switch-mode DC-to-DC converters and low-dropout (LDO) regulators, battery charge management, white LED drivers, low-power stereo audio and voice codecs with a mixer function, Class-D amplifier and headphone driver, a PLL for on-chip and off-chip clock generation, and a touch-screen controller.

The embedded CPU utilizes on-board system management resources, such as instrumentation SAR 12-bit ADC and a real-time clock to provide optimum flexibility while reducing overall system power dissipation. The IDT P95020 PMIC is the first of its kind to integrate all the system power regulation and management functions along with human interface subsystems, such as audio and touch user interfaces.

To help customers design their next-generation devices using the IDT P95020, IDT provides evaluation kits, pre-defined sample scripts and the IDT GUI-based scripting tool.

The IDT P95020 is currently sampling to qualified customers and is available in a 10mm x 10mm, 132-pin QFN package and a 7mm x 7mm WCSP package. The IDT P95020 is priced at $3.72 for 10,000 units.

AMD unlocks 3D Internet potential with OpenGL ES 2.0 driver

SIGGRAPH 2010, LOS ANGELES, USA: AMD has announced availability of the first software driver for desktop computing environments to support the WebGL industry standard, which is designed to bring plugin-free 3D graphics to the Internet.

The AMD OpenGL ES 2.0 driver is intended to help developers easily create exciting 3D content that can be rendered more quickly for consumers using open-source web browsers, thereby helping create an application-like browser experience.

“AMD is a steadfast supporter of industry standards, including those that unlock the power of GPU acceleration,” said Manju Hegde, corporate vice president, AMD Fusion Experience Program.

“At AMD, we see the future of computing as being intensely visual, requiring a variety of rich media 2D and 3D applications. With functionality like the OpenGL ES 2.0 driver and technology breakthroughs made possible by AMD Fusion APUs, we aim to deliver the ideal development platform for immersive experiences both online and natively on virtually any PC form factor.”

In addition to enabling 3D and application-like experiences on the web, AMD’s new driver empowers software developers to use desktop PCs and workstations powered by AMD graphics, as opposed to embedded systems, when creating applications based on OpenGL ES 2.0 for smartphones, tablets and other portable devices.

A common OpenGL ES programming environment makes it easier for developers to port software applications between PCs and handhelds, bringing a seamless computing experience, regardless of device, within our grasp.

Industry association The Khronos Group is developing the open, cross-platform WebGL standard, which is expected to be available later this year. According to Khronos, browser vendors Apple (Safari), Google (Chrome), Mozilla (Firefox), and Opera (Opera) are contributors of the WebGL Working Group.

The OpenGL ES 2.0 driver from AMD will be generally available with the upcoming ATI Catalyst 10.7 beta for OpenGL ES 2.0, expected to be available later today.

The OpenGL ES 2.0 driver will be supported on all currently available AMD graphics products introduced since 2008, including ATI Radeon desktop graphics, ATI Mobility Radeon graphics, and ATI FirePro professional graphics cards.