Real Intent add VHDL checks to Ascent Lint

SAN JOSE, USA: Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, is shipping a new version of Ascent Lint Version 1.3. The new version adds VHDL checks to its existing Verilog checks.

Ascent Lint is the next generation lint tool in Real Intent’s early functional verification family of products. It performs syntax and semantic Hardware Description Language (HDL) lint checks for today’s complex SoC designs. It features an extremely fast engine and low noise report for debugging electronic designs.

Ascent Lint 1.3 adds lint checking for VHDL in the following categories:
• Ambiguous modeling.
• Differences between simulation and synthesis semantics.
• Naming and RTL coding conventions.
• VHDL subset restrictions to enforce modeling clarity and reduce unnecessary complexity.
• Operations with hidden or expensive implementation costs.
• Downstream tool flow issues.
• Network and connectivity checks for clocks, resets, and tristate-driven signals.
• Testability.

“The customer response to the initial deployments of Ascent Lint has been universally very positive,” commented Pranav Ashar, Chief Technology Officer at Real Intent. “The feedback is that it is extremely easy to set up and more than an order of magnitude faster than competitive products. Ascent Lint 1.3 builds on this platform to deliver VHDL support. In addition, a key focus in this release has been to deliver an unprecedented level of usability. We are confident that with this combination of very high performance and usability, Ascent Lint 1.3 will provide compelling value in the front-end of any verification flow.”

Ascent Lint 1.3 is available now.