Parallel Engines launches world’s largest semiconductor-IP directory for FPGAs

CUPERTINO, USA: Parallel Engines Corp. has announced the public availability of www.FPGAIPDirectory.com, indexing over 17,000 IP blocks and FPGA devices.

Customers can search for Semiconductor-IP and retrieve IP Vendor datasheets, IP meta-information, and FPGA device configurations. Meta-information includes IP interfaces, LUT, BRAM, I/O and embedded IP resources, costs and packages.

Parallel Engines is the brainchild of George Janac, Electronic Design Automation pioneer, founder of Chip Estimate; High Level Design Systems, and startup investor. “FPGA design has long been served by a disaggregated IP supply chain,” said Janac.

“Our goal is to change that. We are integrating many elements to bring EDA and IP together for FPGA. With 28nm FPGA devices coming into production, designers will struggle even more with implementation methodology choices and cost effectiveness.”

Parallel Engines has aggregated over 4,000 Soft-IP blocks and Embedded Hard-IP from over 300 vendors along with Verification and Software IP. www.FPGAIPDirectory.com includes FPGA devices from Xilinx, Altera, Actel and Lattice Semiconductor. Customers can find information on both IP and devices. Subscription customers will be able to access data for pricing, configurations, AMBA, AXI, AHB, OCP, interfaces, I/O standards, packages, power, etc.

Parallel Engines is also announcing expansion of its beta program for its Platform Specification system, FpgaRFQ (standing for FPGA Request-for-Quote). This system allows the definition of a FPGA Platforms based on IP content. Platforms can then optimally fit into one or more FPGA devices. In its final release form, this system will enable designers to find the optimal FPGA parts providing cost, power, design guidance, and ASIC versus FPGA tradeoffs.

Next Generation design will be standards based. On-Chip Busses, in the form of Network-on-Chip or Fabric will connect ever larger IP based subsystems. “FPGA, in production or ASIC prototyping, is the ideal vehicle for this design style,” said Janac.

“The combination of FPGAIPDirectory, FpgaRFQ, Standards, with Network-on-Chip Planning (part of FpgaRFQ) brings everything into one place.” Designers will see reduced time to market and reduced risk, while minimizing costs. Today FPGAIPDirectory contains over 600 IPs with standard on-chip connectors.

The company plans to announce, and release, additional products over the next two months.