Dr. Robert N. Castellano, The Information Network
NEW TRIPOLI, USA: Multiple technologies are being explored to form vias during the wafer fabrication process (front-end) and the IC packaging and assembly stage (back-end). Metrology and inspection of the TSVs are critical for ensuring the performance of the 3D ICs and the profitability of the overall manufacturing process.
Interest in 3D interconnect, including TSVs, continues to increase. As with any new process technology, there are many interesting measurement challenges associated with 3D interconnect, including important issues facing TSV processing. Examples include voids and other defects between bonded wafers, overlay between wafers, and the impact of stress on the TSVs themselves.
A list of TSV measurement needs includes:
* TSV Depth and Profile through multiple layers.
* Alignment of chips for stacking – wafer level integration.
* Bond strength.
* Defects in bonding.
* Damage to metal layers.
* Defects in vias between wafers.
* Through Si via is a high aspect ratio CD issue,
* Wafer thickness and TTV after thinning.
* Defects after thinning including wafer edge.
In our latest report 3-D TSV: Insight On Critical Issues And Market Analysis, our analysis shows that while the overall equipment market will grow at a CAGR of nearly 60 percent between 2008-2013, the metrology/inspection sector is expected to grow nearly 80 percent.
On the device side, TSVs for MEMS is expected to grow nearly 100 percent in this time frame.