SAN JOSE, USA: Cadence Design Systems Inc. has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs.
Cadence donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.
“We thank Cadence for this significant and timely contribution to Accellera,” said Shrenik Mehta, chair of Accellera. “We welcome this new technology aimed at strengthening our Verilog-AMS standard, which is critical for engineers tasked with conducting efficient, yet deep, verification on some of today’s most complex chips.”
“As the industry leader in mixed-signal design enablement, we are contributing this open-format wreal technology to enable the development of interoperable solutions to meet the needs of our industry,” said Sandeep Mehndiratta, solutions marketing group director at Cadence.
“With the ability to conduct mixed-signal verification at digital speeds—even running nightly regression tests—we are confident verification teams will see significant benefits from deploying this technology.”