Synopsys universal DDR controllers improve performance, reduce cost of embedded DRAM interfaces

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of the high-performance DesignWare® Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards.

The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys’ previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs.

The DesignWare Universal Protocol Controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133 Mbps, the maximum data rate of the DDR3 standard, and offer a broadly utilized DFI 2.1-compliant interface to the DDR PHY.

Furthermore, the Universal DDR Memory and Protocol Controllers enable designers to easily integrate multiple DDR interfaces into one design servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive with less risk and improved time-to-market.

The multi-port DesignWare Universal DDR Memory Controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. In addition, the DesignWare Universal DDR Memory Controller provides high memory bandwidth utilization through transaction reordering, bandwidth allocation per port, and quality-of-service (QoS) based arbitration for latency-sensitive and/or high-bandwidth traffic.

Complementing the DesignWare DDR Universal Memory Controller, the unique single-port DesignWare Universal DDR Protocol Controller is designed to optimize memory channel bandwidth utilization with reduced latency, allowing designers to implement a custom memory scheduler that is optimized for specific DRAM traffic patterns.

The DesignWare Universal DDR Protocol Controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in high-speed, general purpose process technologies and ease of timing closure in low power process technologies.

“As a fabless semiconductor company that pushes the limits of general purpose multicore processing to the highest performance per watt per silicon area, we need an established IP vendor that would enable us to optimize the throughput and latency of high-end DDR memory solutions” said Peleg Aviely, CTO at Plurality Ltd.

“After evaluating different IP vendors, we selected Synopsys based on their track record of delivering high-quality, silicon-proven DesignWare DDR IP solutions that are backed by a knowledgeable technical support team.”

“As DDR SDRAM standards continue to proliferate, it is vital to provide designers with a DDR IP solution that can support the breadth of SDRAM options,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The new DesignWare Universal DDR protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimizing the utilization of the memory channel bandwidth.”

The DesignWare Universal DDR protocol and memory controllers are part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.

The DesignWare Universal DDR protocol and memory controllers as well as the complementary PHYs are available now.