SAN JOSE, USA: Samsung Electronics Co. Ltd is ramping up 40-nm class production of high-density DDR3 memory chips to accommodate increased demand in server applications.
The recent launch of Intel's Xeon processor 5600 Series, as well as the introduction of Xeon 7500 processors support the growing industry demand for enhanced performance and low power platform solutions, especially when paired with DDR3 memory.
Samsung’s DDR3 enables OEMs to use up to 192 gigabytes (GBs) on a Xeon 5500 platform (16GBx12) with at least a 73 percent improvement in power consumption at 1.35 volts, when accompanied by the Xeon 5600 processor. DDR3 has double the memory bandwidth of DDR2, with speeds up to 1333 Megabits per second (Mbps).
With the new Xeon 7500 platform, OEMs can use up to 1 terabyte per 4-socket system and with more sockets, can easily scale to memory densities 2 TBs and higher. Later this year, Samsung’s 4 Gigabit (Gb) DDR3 chips and modules also will be available for use with the latest Xeon platforms and processors.
“When used in conjunction with use of the Xeon processor 5600 series and the 5500 and 7500 platforms, DDR3 is designed to dramatically improve the efficiency of data transactions while lowering power consumption in virtually any enterprise server application,” said Jim Elliott, vice president, memory marketing, Samsung Semiconductor, Inc. “Our low-power DDR3 solutions will play a pivotal role in advancing the design of new-generation, ‘green’ servers,” he added.
“We have been working closely with Samsung to advance the importance of green memory in the data center,” said Lorie Wigle, General Manager, Intel Eco-Technology Office. “Our new multi-core Xeon lines have been designed to not only accommodate the most energy-efficient memory in the market today, but also to provide IT managers with the best power-to-performance ratio for any server environment.”
Samsung’s DDR3 supports the high-performance, low power requirements of a wide range of server applications such as streaming media content delivery, on-line transaction processing internet data centers, and virtualization in data centers, as well as future cloud computing architectures.
Samsung’s DDR3 devices include 1Gb, 2Gb and 4Gb DRAM chips, as well as 1GB, 2GB, 4GB, 8GB, 16GB and 32GB registered DIMMs (dual in-line memory modules) and 1GB, 2GB, 4GB and 8GB ECC unbuffered DIMMs.
The advanced 40nm-class DDR3 chips are available at speeds of 800 megabit per second (Mbps), 1066Mbps, 1333Mbps and 1600Mbps and can offer up to a 40 percent power savings at 1333Mbps, compared to 60nm-class DDR3 chips.
Friday, April 30, 2010
IXYS, Zilog intro digital power control reference designs that feature IXYS power semiconductors and Zilog MCUs
BIEL, SWITZERLAND: IXYS Corp., a leader in power semiconductors and mixed signal ICs and MCUs for improved power management, energy efficiency and renewable energy, have introduced new reference designs that will be demonstrated in the PCIM Europe 2010 show in Nuremberg Germany in the IXYS Booth 12/401.
The Motor Control reference designs feature the Z8 Encore! Z8FMC16100 MCU and a brushless DC motor. A motion sensing and control design features the Zilog ZMOTIONTM with technology, based on a passive infrared sensor and the Z8 Encore! Z8FO82A microcontroller. For advanced LED lighting control, the Z8 Encore! XP Z8F1680 microcontroller based design that controls an IXYS LED driver LDS8720 driving 32 LEDs that is powered by the IXYS solar cells will also be demonstrated.
“We are delighted to bring to Europe the innovative spirit of Silicon Valley, with the integration of our power semiconductors and the Zilog world renowned MCUs. The demonstration will feature the use of the Apple iPad as an advanced control and demonstration platform by our Zilog team headed by Darin Billerbeck, CEO of Zilog,” commented Dr. Nathan Zommer, CEO of IXYS.
The Motor Control reference designs feature the Z8 Encore! Z8FMC16100 MCU and a brushless DC motor. A motion sensing and control design features the Zilog ZMOTIONTM with technology, based on a passive infrared sensor and the Z8 Encore! Z8FO82A microcontroller. For advanced LED lighting control, the Z8 Encore! XP Z8F1680 microcontroller based design that controls an IXYS LED driver LDS8720 driving 32 LEDs that is powered by the IXYS solar cells will also be demonstrated.
“We are delighted to bring to Europe the innovative spirit of Silicon Valley, with the integration of our power semiconductors and the Zilog world renowned MCUs. The demonstration will feature the use of the Apple iPad as an advanced control and demonstration platform by our Zilog team headed by Darin Billerbeck, CEO of Zilog,” commented Dr. Nathan Zommer, CEO of IXYS.
Major growth in TSV metrology/inspection equipment expected
Dr. Robert N. Castellano, The Information Network
NEW TRIPOLI, USA: Multiple technologies are being explored to form vias during the wafer fabrication process (front-end) and the IC packaging and assembly stage (back-end). Metrology and inspection of the TSVs are critical for ensuring the performance of the 3D ICs and the profitability of the overall manufacturing process.
Interest in 3D interconnect, including TSVs, continues to increase. As with any new process technology, there are many interesting measurement challenges associated with 3D interconnect, including important issues facing TSV processing. Examples include voids and other defects between bonded wafers, overlay between wafers, and the impact of stress on the TSVs themselves.
A list of TSV measurement needs includes:
* TSV Depth and Profile through multiple layers.
* Alignment of chips for stacking – wafer level integration.
* Bond strength.
* Defects in bonding.
* Damage to metal layers.
* Defects in vias between wafers.
* Through Si via is a high aspect ratio CD issue,
* Wafer thickness and TTV after thinning.
* Defects after thinning including wafer edge.
In our latest report 3-D TSV: Insight On Critical Issues And Market Analysis, our analysis shows that while the overall equipment market will grow at a CAGR of nearly 60 percent between 2008-2013, the metrology/inspection sector is expected to grow nearly 80 percent.
On the device side, TSVs for MEMS is expected to grow nearly 100 percent in this time frame.
NEW TRIPOLI, USA: Multiple technologies are being explored to form vias during the wafer fabrication process (front-end) and the IC packaging and assembly stage (back-end). Metrology and inspection of the TSVs are critical for ensuring the performance of the 3D ICs and the profitability of the overall manufacturing process.
Interest in 3D interconnect, including TSVs, continues to increase. As with any new process technology, there are many interesting measurement challenges associated with 3D interconnect, including important issues facing TSV processing. Examples include voids and other defects between bonded wafers, overlay between wafers, and the impact of stress on the TSVs themselves.
A list of TSV measurement needs includes:
* TSV Depth and Profile through multiple layers.
* Alignment of chips for stacking – wafer level integration.
* Bond strength.
* Defects in bonding.
* Damage to metal layers.
* Defects in vias between wafers.
* Through Si via is a high aspect ratio CD issue,
* Wafer thickness and TTV after thinning.
* Defects after thinning including wafer edge.
In our latest report 3-D TSV: Insight On Critical Issues And Market Analysis, our analysis shows that while the overall equipment market will grow at a CAGR of nearly 60 percent between 2008-2013, the metrology/inspection sector is expected to grow nearly 80 percent.
On the device side, TSVs for MEMS is expected to grow nearly 100 percent in this time frame.
ASM International books repeat orders for plasma enhanced ALD systems
ALMERE, THE NETHERLANDS: ASM International N.V. has received multiple repeat orders this year for its plasma enhanced atomic layer deposition (PEALD) systems from a leading memory customer in Asia for volume manufacturing at multiple fab lines.
All systems will be used for dielectrics in double patterning applications for advanced lithography at the 3X technology node and below.
Additionally, ASM is expanding developments for PEALD dielectrics for logic transistor gate protection applications at the 22 nm node. As part of this development program, PEALD tools have been delivered to multiple advanced logic customers.
"PEALD is increasingly being adopted due to its ability to control deposition one atomic layer at a time on a wide range of device structures," said Tominori Yoshida, General Manager of ASM's Plasma Products product group. "We have made very good progress in developing PEALD as an enabling technology for new dielectrics applications. Our patent position in PEALD should enable us to fully benefit from the broad range of new applications in the challenging 2X and 1X nodes."
The PEALD reactors are optimized to deposit dielectrics including SiO, SiN and SiCN. A major advantage of ASM's PEALD process is its ability to deliver conformal thin films at low temperatures, which is especially beneficial for double patterning lithography technologies where thin dielectrics are deposited over temperature sensitive photoresists for critical dimension control and pitch reduction.
Each one of the systems ordered includes multiple PEALD reactors implemented on ASM's Eagle XP platform, the company's production-proven standard platform that can be configured with plasma enhanced chemical vapor deposition (PECVD), Thermal ALD or PEALD reactors.
All systems will be used for dielectrics in double patterning applications for advanced lithography at the 3X technology node and below.
Additionally, ASM is expanding developments for PEALD dielectrics for logic transistor gate protection applications at the 22 nm node. As part of this development program, PEALD tools have been delivered to multiple advanced logic customers.
"PEALD is increasingly being adopted due to its ability to control deposition one atomic layer at a time on a wide range of device structures," said Tominori Yoshida, General Manager of ASM's Plasma Products product group. "We have made very good progress in developing PEALD as an enabling technology for new dielectrics applications. Our patent position in PEALD should enable us to fully benefit from the broad range of new applications in the challenging 2X and 1X nodes."
The PEALD reactors are optimized to deposit dielectrics including SiO, SiN and SiCN. A major advantage of ASM's PEALD process is its ability to deliver conformal thin films at low temperatures, which is especially beneficial for double patterning lithography technologies where thin dielectrics are deposited over temperature sensitive photoresists for critical dimension control and pitch reduction.
Each one of the systems ordered includes multiple PEALD reactors implemented on ASM's Eagle XP platform, the company's production-proven standard platform that can be configured with plasma enhanced chemical vapor deposition (PECVD), Thermal ALD or PEALD reactors.
Dr. Biswadip (Bobby) Mitra takes charge as ISA chairman for 2010-11
BANGALORE, INDIA: Dr. Biswadip (Bobby) Mitra, president and managing director, Texas Instruments India is the new chairman and Dr. Pradip K Dutta, corporate VP and managing director, Synopsis India, has been elected as the Vice Chairman of India Semiconductor Association (ISA) for the year 2010-11. Ms. Poornima Shenoy is the President of ISA.
Widely acknowledged for his leadership in the industry, Dr. Mitra takes charge at a time when ISA is poised to play a key role in driving rapid growth of the Indian electronics industry.
Dr. Mitra said: “The electronics System Design and Manufacturing (ESDM) is a huge opportunity for India. It also has the potential to change our country. Through strong acceleration by the ISA member community, we aim to fast-forward the growth across multiple verticals, driven by the electronics system design and manufacturing companies. We will also intensify our focus on green energy leadership and inclusive growth.”
“We have strong ISA membership from 130 companies in the semiconductor ecosystem today. Moving forward, we expect to have several more OEMs in ISA who are engaged in systems design and manufacturing in India. These OEMs will propel our industry’s future electronics growth,” he added.
The members of the ISA Executive Council for 2010-11 are:
• Dr. Biswadip (Bobby) Mitra, President & Managing Director, Texas Instruments
India (ISA Chairman).
• Dr. Pradip K Dutta, Corporate VP & Managing Director, Synopsis India (ISA Vice Chairman).
• Rajesh Mishra, VP, SEMI & Peripherals Practice, Wipro Technologies (ISA Treasurer).
• B.V. Naidu, Adviser, ISA and Chairman, Sagitaur Ventures.
• Ms. Poornima Shenoy, ISA President.
• Dr. Satyanarayan Gupta, CEO, Concept2Silicon Systems.
• Ganesh Guruswamy, VP & Country Manager, Freescale Semiconductor.
• Praveen Vishakantaiah, President, Intel India.
• Raghu Panicker, Sales Director, Mentor Graphics India.
• Vivek Sharma, EMR VP & Director, India Design Center, ST Microelectronics.
• Sanjay Nayak, CEO, Tejas Networks.
Widely acknowledged for his leadership in the industry, Dr. Mitra takes charge at a time when ISA is poised to play a key role in driving rapid growth of the Indian electronics industry. Dr. Mitra said: “The electronics System Design and Manufacturing (ESDM) is a huge opportunity for India. It also has the potential to change our country. Through strong acceleration by the ISA member community, we aim to fast-forward the growth across multiple verticals, driven by the electronics system design and manufacturing companies. We will also intensify our focus on green energy leadership and inclusive growth.”
“We have strong ISA membership from 130 companies in the semiconductor ecosystem today. Moving forward, we expect to have several more OEMs in ISA who are engaged in systems design and manufacturing in India. These OEMs will propel our industry’s future electronics growth,” he added.
The members of the ISA Executive Council for 2010-11 are:
• Dr. Biswadip (Bobby) Mitra, President & Managing Director, Texas Instruments
India (ISA Chairman).
• Dr. Pradip K Dutta, Corporate VP & Managing Director, Synopsis India (ISA Vice Chairman).
• Rajesh Mishra, VP, SEMI & Peripherals Practice, Wipro Technologies (ISA Treasurer).
• B.V. Naidu, Adviser, ISA and Chairman, Sagitaur Ventures.
• Ms. Poornima Shenoy, ISA President.
• Dr. Satyanarayan Gupta, CEO, Concept2Silicon Systems.
• Ganesh Guruswamy, VP & Country Manager, Freescale Semiconductor.
• Praveen Vishakantaiah, President, Intel India.
• Raghu Panicker, Sales Director, Mentor Graphics India.
• Vivek Sharma, EMR VP & Director, India Design Center, ST Microelectronics.
• Sanjay Nayak, CEO, Tejas Networks.
ST delivers all-round efficiency gains with smallest four-line ESD protection IC
GENEVA, SWITZERLAND: STMicroelectronics has unveiled an IC for use with today's highest-speed multimedia and storage interconnects, including HDMI, DisplayPort, USB 3.0, Serial ATA (SATA) and DVI.
The new device provides ESD protection for four data lines within a 1x2mm-outline package, saving at least 30% of PCB space compared to other devices.
As these high-speed interconnect standards maximize ease of use – specifying convenient, miniaturized connectors and cables – consumers can easily connect and disconnect devices such as high-definition video equipment, terabyte storage, multi-megapixel cameras, and personal media devices including smartphones.
This increases the risk of damage to internal circuitry by electrostatic discharges (ESD), which can occur when a device is touched or when a cable is connected or removed.
By providing a convenient one-chip ESD-protection solution, ST's HSP061-4NY8 addresses a large and important market: total worldwide shipments of equipment containing an HDMI or DisplayPort connection, for example, are expected to exceed one billion units by 2012, according to industry analysts.
The HSP061-4NY8 provides the industry with a single orderable part capable of protecting circuits using any of these multi-gigabit standards, enabling economies of scale as well as significant advantages in efficiency throughout product design, purchasing, and assembly.
The device contains a network of Transient Voltage Suppression (TVS) diodes capable of protecting two pairs of high-speed differential data lines. These diodes are sufficient to provide complete protection for the 5.0 Gbit/s SuperSpeed bus defined in the new USB 3.0 specification.
A single HSP061-4NY8 can also protect all the data lines of an HDMI port, an entire channel in SATA interfaces, up to and including the latest 6Gbit/s SATA 3.0 standard, or a two-lane DisplayPort interface.
The new device provides ESD protection for four data lines within a 1x2mm-outline package, saving at least 30% of PCB space compared to other devices.
As these high-speed interconnect standards maximize ease of use – specifying convenient, miniaturized connectors and cables – consumers can easily connect and disconnect devices such as high-definition video equipment, terabyte storage, multi-megapixel cameras, and personal media devices including smartphones.
This increases the risk of damage to internal circuitry by electrostatic discharges (ESD), which can occur when a device is touched or when a cable is connected or removed.
By providing a convenient one-chip ESD-protection solution, ST's HSP061-4NY8 addresses a large and important market: total worldwide shipments of equipment containing an HDMI or DisplayPort connection, for example, are expected to exceed one billion units by 2012, according to industry analysts.
The HSP061-4NY8 provides the industry with a single orderable part capable of protecting circuits using any of these multi-gigabit standards, enabling economies of scale as well as significant advantages in efficiency throughout product design, purchasing, and assembly.
The device contains a network of Transient Voltage Suppression (TVS) diodes capable of protecting two pairs of high-speed differential data lines. These diodes are sufficient to provide complete protection for the 5.0 Gbit/s SuperSpeed bus defined in the new USB 3.0 specification.
A single HSP061-4NY8 can also protect all the data lines of an HDMI port, an entire channel in SATA interfaces, up to and including the latest 6Gbit/s SATA 3.0 standard, or a two-lane DisplayPort interface.
PC MPU unit shipments experience modest sequential decline in Q1, rise 39pc YoY
SAN MATEO, USA: Worldwide PC microprocessor unit shipments in the first calendar quarter of 2010 (1Q10) declined 5.6 percent compared to 4Q09, according to the latest PC processor study from IDC.
A decline between a calendar year's fourth quarter and the next calendar year's first quarter is typical of seasonal demand patterns but this decline is less than normal. When compared to 1Q09, shipments in 1Q10 rose 39 percent. Total market revenue in 1Q10 fell 2 percent compared to 4Q09 and rose 40.4 percent compared to 1Q09.
"PC processor shipments typically decline around 7 to 8 percent going from fourth quarter to first quarter," said Shane Rau director of Semiconductors: Personal Computing research at IDC. "A decline of 5.6 percent is modest and wouldn't mean much by itself. However, after the huge rise in shipments we saw in the fourth quarter, it adds more credibility to market recovery and that the PC industry anticipates improvement in PC end demand in 2010."
Looking at market performance by PC form factor, mobile PC processors declined 6.3 percent quarter over quarter, desktop PC processors declined 5.1 percent quarter over quarter, and PC server processors declined 1.4 percent quarter over quarter.
The overall market average selling price in 1Q10 rose 4.1 percent quarter over quarter due to more high-end processors in the total mix compared to 4Q09. Notably, Intel's low-end Atom processor for mininotebooks (also known as netbooks) represented 20 percent of Intel's mobile PC processor mix in 1Q10, which is down from 24 percent in 4Q09.
"Intel's new Core processors and AMD's new Athlon processors are ramping, and at a time when, IDC believes, consumers and corporations will be anticipating a much healthier 2010 and looking for more value than just low price in their PCs," added Rau. "In terms of the processor, that means more openness to paying for benefits such as good performance and reduced power consumption that serves long battery life."
1Q10 vendor highlights
In 1Q10, Intel earned 81 percent unit market share, a gain of 0.5 percent, while AMD earned 18.8 percent, a loss of 0.6 percent, and VIA Technologies earned 0.2 percent.
In 1Q10 by form factor, Intel earned 87.8 percent share in the mobile PC processor segment, a gain of 0.5 percent. AMD finished the quarter with 12.1 percent, a loss of 0.6 percent, and VIA earned 0.1 percent.
In the PC server/workstation processor segment, Intel finished with 90.2 percent market share, a gain of 0.4 percent and AMD earned 9.8 percent, a loss of 0.4 percent. In the desktop PC processor segment, Intel earned 71.7 percent, a gain of 0.6 percent, AMD earned 28 percent, a loss of 0.7 percent, and VIA earned 0.3 percent.
Market outlook
IDC's forecast for worldwide PC processor unit growth in 2010 is 15.1 percent. However, the results of 1Q10, low inventories, strong outlooks from PC semiconductor vendors and some PC OEMs, and a generally positive outlook for consumer and corporate IT spending for the rest of the year, are strong signs for additional growth.
"IDC will be watching 2Q10 very closely," said Rau. "Specifically, we'll be watching for the expected improvement in corporate IT spending and talking to PC component suppliers to make sure that, after a long period of anemic capital expenditures, they believe end demand is solid and are bringing new capacity online."
A decline between a calendar year's fourth quarter and the next calendar year's first quarter is typical of seasonal demand patterns but this decline is less than normal. When compared to 1Q09, shipments in 1Q10 rose 39 percent. Total market revenue in 1Q10 fell 2 percent compared to 4Q09 and rose 40.4 percent compared to 1Q09.
"PC processor shipments typically decline around 7 to 8 percent going from fourth quarter to first quarter," said Shane Rau director of Semiconductors: Personal Computing research at IDC. "A decline of 5.6 percent is modest and wouldn't mean much by itself. However, after the huge rise in shipments we saw in the fourth quarter, it adds more credibility to market recovery and that the PC industry anticipates improvement in PC end demand in 2010."
Looking at market performance by PC form factor, mobile PC processors declined 6.3 percent quarter over quarter, desktop PC processors declined 5.1 percent quarter over quarter, and PC server processors declined 1.4 percent quarter over quarter.
The overall market average selling price in 1Q10 rose 4.1 percent quarter over quarter due to more high-end processors in the total mix compared to 4Q09. Notably, Intel's low-end Atom processor for mininotebooks (also known as netbooks) represented 20 percent of Intel's mobile PC processor mix in 1Q10, which is down from 24 percent in 4Q09.
"Intel's new Core processors and AMD's new Athlon processors are ramping, and at a time when, IDC believes, consumers and corporations will be anticipating a much healthier 2010 and looking for more value than just low price in their PCs," added Rau. "In terms of the processor, that means more openness to paying for benefits such as good performance and reduced power consumption that serves long battery life."
1Q10 vendor highlights
In 1Q10, Intel earned 81 percent unit market share, a gain of 0.5 percent, while AMD earned 18.8 percent, a loss of 0.6 percent, and VIA Technologies earned 0.2 percent.
In 1Q10 by form factor, Intel earned 87.8 percent share in the mobile PC processor segment, a gain of 0.5 percent. AMD finished the quarter with 12.1 percent, a loss of 0.6 percent, and VIA earned 0.1 percent.
In the PC server/workstation processor segment, Intel finished with 90.2 percent market share, a gain of 0.4 percent and AMD earned 9.8 percent, a loss of 0.4 percent. In the desktop PC processor segment, Intel earned 71.7 percent, a gain of 0.6 percent, AMD earned 28 percent, a loss of 0.7 percent, and VIA earned 0.3 percent.
Market outlook
IDC's forecast for worldwide PC processor unit growth in 2010 is 15.1 percent. However, the results of 1Q10, low inventories, strong outlooks from PC semiconductor vendors and some PC OEMs, and a generally positive outlook for consumer and corporate IT spending for the rest of the year, are strong signs for additional growth.
"IDC will be watching 2Q10 very closely," said Rau. "Specifically, we'll be watching for the expected improvement in corporate IT spending and talking to PC component suppliers to make sure that, after a long period of anemic capital expenditures, they believe end demand is solid and are bringing new capacity online."
Xilinx announces record Q4 sales of $529 million
SAN JOSE, USA: Xilinx Inc. has announced fiscal 2010 sales of $1.83 billion, essentially flat with sales from the prior fiscal year.
Fiscal 2010 net income decreased 1% to $357.5 million, or $1.29 per diluted share, versus fiscal 2009 net income of $361.7 million, or $1.31 per diluted share. Fiscal 2009 net income included a $75 million pre-tax gain, or $0.21 per diluted share, on the extinguishment of convertible debt.
Fourth quarter fiscal 2010 sales were $529 million, up 3 percent sequentially and up 34 percent from the fourth quarter of the prior fiscal year. Fourth quarter fiscal 2010 net income was $148.5 million, or $0.54 per diluted share, including previously announced pre-tax restructuring charges totaling $2.8 million, or $0.01 per diluted share.
Included in the fourth quarter net income was a tax benefit of $23.2 million, or $0.08 per diluted share, primarily related to the impact of our recent favorable ruling in the Ninth Circuit Court.
The Xilinx Board of Directors announced a quarterly cash dividend of $0.16 per outstanding share of common stock, payable on June 9, 2010 to all stockholders of record at the close of business on May 19, 2010.
Fiscal 2010 net income decreased 1% to $357.5 million, or $1.29 per diluted share, versus fiscal 2009 net income of $361.7 million, or $1.31 per diluted share. Fiscal 2009 net income included a $75 million pre-tax gain, or $0.21 per diluted share, on the extinguishment of convertible debt.
Fourth quarter fiscal 2010 sales were $529 million, up 3 percent sequentially and up 34 percent from the fourth quarter of the prior fiscal year. Fourth quarter fiscal 2010 net income was $148.5 million, or $0.54 per diluted share, including previously announced pre-tax restructuring charges totaling $2.8 million, or $0.01 per diluted share.
Included in the fourth quarter net income was a tax benefit of $23.2 million, or $0.08 per diluted share, primarily related to the impact of our recent favorable ruling in the Ninth Circuit Court.
The Xilinx Board of Directors announced a quarterly cash dividend of $0.16 per outstanding share of common stock, payable on June 9, 2010 to all stockholders of record at the close of business on May 19, 2010.
2010 semicon market outlook update: Databeans revises chip forecast
USA: All signs are pointing to a stronger second quarter than originally predicted. Databeans current outlook for the chip industry for 2010 has been revised up to $277 billion, a 23 percent increase over 2009.
We expect microprocessor and logic revenue this year to reach over $41 billion and $76 billion respectively. Memory revenue, driven by ongoing demand in the Flash market and higher prices for DRAM, is expected to reach close to $61 billion. And after surveying several of the large analog suppliers, Databeans now expects this market to come in at $41 billion, an increase of 28 percent over 2009.
For the second quarter, sequential growth for these key markets driving the overall semiconductor industry is expected. Microprocessor revenue is expected to end the quarter at $10.5 billion a 3 percent increase from the first quarter. Logic is expected to be up 7 percent, memory up 4 percent, and general purpose analog is expected to grow by over 8 percent in the second quarter.
Inventory stocking is completed and we believe this growth is driven by the current demand in the end markets for consumer products including wireless devices as well as industrial application markets. The computer replacement cycle has been long overdue and will continue to add to demand although we are expecting some drop off for memory in the third quarter because of the higher prices as PC OEMs could cut back on what they offer consumers in the mid-range platforms.
Worldwide Semiconductor Revenue Forecast by Product Type
Databeans Estimates
We expect microprocessor and logic revenue this year to reach over $41 billion and $76 billion respectively. Memory revenue, driven by ongoing demand in the Flash market and higher prices for DRAM, is expected to reach close to $61 billion. And after surveying several of the large analog suppliers, Databeans now expects this market to come in at $41 billion, an increase of 28 percent over 2009.
For the second quarter, sequential growth for these key markets driving the overall semiconductor industry is expected. Microprocessor revenue is expected to end the quarter at $10.5 billion a 3 percent increase from the first quarter. Logic is expected to be up 7 percent, memory up 4 percent, and general purpose analog is expected to grow by over 8 percent in the second quarter.
Inventory stocking is completed and we believe this growth is driven by the current demand in the end markets for consumer products including wireless devices as well as industrial application markets. The computer replacement cycle has been long overdue and will continue to add to demand although we are expecting some drop off for memory in the third quarter because of the higher prices as PC OEMs could cut back on what they offer consumers in the mid-range platforms.
Worldwide Semiconductor Revenue Forecast by Product Type
Databeans Estimates
NetLogic, TSMC collaborate on 28nm process technology
MOUNTAIN VIEW, USA: NetLogic Microsystems Inc. and TSMC announced an extension of their long-standing collaboration to include TSMC’s NEXSYS 28HP (28nm high performance) semiconductor process node for NetLogic Microsystems’ next-generation knowledge-based processors, multi-core processors and 10/40/100Gigabit PHY.
As an early development partner, NetLogic Microsystems is using TSMC’s 28nm node to raise the networking infrastructure performance bar, and therefore significantly differentiating its product line from the competition.
NetLogic Microsystems has launched advanced product development for multiple industry-leading product lines on the TSMC 28nm node. The 28HP process offers significant speed, and power efficiency advantages over previous process nodes.
In addition, NetLogic Microsystems is developing a suite of custom high-performance circuits optimized around TSMC’s 28nm node, including high-speed serial interface technology, analog and clocking circuitry, core processing elements and other standard cells, as well as refining the design and tape-out flow for this advanced node.
“By being a consistent early adopter across four generations of process technology, NetLogic Microsystems has consistently provided very high performance and low power products for mission-critical network infrastructure systems,” said Rick Cassidy, president of TSMC North America. “We welcome the extension of our close relationship to include NetLogic Microsystems’ role as an 28nm early technology adopter.”
“We are proud to have been one of the early partners for TSMC in 80nm, 55nm, 40nm and now 28nm for our best-in-class knowledge-based processors, multi-core processors and 10/40/100 Gigabit PHY product families,” said Ron Jankov, president and CEO at NetLogic Microsystems.
“By combining the superior design and architecture of our products with TSMC’s proven leadership and track record in advanced manufacturing technologies, we are able to deliver highly innovative products with unprecedented performance, scalability and energy efficiency to our customers.”
NetLogic Microsystems offers high-performance multi-core, multi-threaded processors, knowledge-based processors, content processors, and high-speed 10/40/100 Gigabit Ethernet PHY solutions.
These market-leading products are designed into high-performance systems such as switches, routers, wireless base stations, security appliances, networked storage appliances and service gateways to significantly enhance the performance and functionality of next-generation 3G/4G mobile wireless infrastructure, data center, enterprise, metro Ethernet, edge and core infrastructure networks.
As an early development partner, NetLogic Microsystems is using TSMC’s 28nm node to raise the networking infrastructure performance bar, and therefore significantly differentiating its product line from the competition.
NetLogic Microsystems has launched advanced product development for multiple industry-leading product lines on the TSMC 28nm node. The 28HP process offers significant speed, and power efficiency advantages over previous process nodes.
In addition, NetLogic Microsystems is developing a suite of custom high-performance circuits optimized around TSMC’s 28nm node, including high-speed serial interface technology, analog and clocking circuitry, core processing elements and other standard cells, as well as refining the design and tape-out flow for this advanced node.
“By being a consistent early adopter across four generations of process technology, NetLogic Microsystems has consistently provided very high performance and low power products for mission-critical network infrastructure systems,” said Rick Cassidy, president of TSMC North America. “We welcome the extension of our close relationship to include NetLogic Microsystems’ role as an 28nm early technology adopter.”
“We are proud to have been one of the early partners for TSMC in 80nm, 55nm, 40nm and now 28nm for our best-in-class knowledge-based processors, multi-core processors and 10/40/100 Gigabit PHY product families,” said Ron Jankov, president and CEO at NetLogic Microsystems.
“By combining the superior design and architecture of our products with TSMC’s proven leadership and track record in advanced manufacturing technologies, we are able to deliver highly innovative products with unprecedented performance, scalability and energy efficiency to our customers.”
NetLogic Microsystems offers high-performance multi-core, multi-threaded processors, knowledge-based processors, content processors, and high-speed 10/40/100 Gigabit Ethernet PHY solutions.
These market-leading products are designed into high-performance systems such as switches, routers, wireless base stations, security appliances, networked storage appliances and service gateways to significantly enhance the performance and functionality of next-generation 3G/4G mobile wireless infrastructure, data center, enterprise, metro Ethernet, edge and core infrastructure networks.
IDT announces first high-accuracy all-Silicon CMOS oscillators in package and die/wafer form
SAN JOSE, USA: Integrated Device Technology Inc. (IDT) has announced the availability of its all-silicon CMOS oscillators, the MM8202 and the MM8102 in wafer and package forms, making IDT the only company to offer quartz-crystal-level performance with a CMOS oscillator in both forms.
These ICs eliminate quartz-based resonators and oscillators in consumer, computation and storage applications with small form factor requirements and offer excellent link performance for all generations of common serial wireline interfaces, including S-ATA, PCIe, USB 2.0 and USB 3.0. The wafer form availability of the product enables chip-on-board (CoB) and multi-chip module (MCM) assembly designs for significant space savings.
The MM8202 and MM8102 are built on standard CMOS technology and do not require any mechanical frequency references, be it quartz or MEMS, offering IDT customers a fully integrated alternative to quartz-based resonators and oscillators. In addition, the MM8202 is ideal for thin profile consumer devices, such as high-capacity SIM cards and USB Flash drives.
“IDT is the first and only company to offer quartz-crystal-level performance with a CMOS oscillator in wafer form with high frequency accuracy,” said Michael McCorquodale, general manager of the IDT Silicon Frequency Control (SFC) business.
“Replacement of quartz crystals with our wire-bondable CMOS oscillator is a major breakthrough for form-factor-sensitive designs. It enables cost-effective CoB assembly for USB Flash drives, card readers and many other consumer applications. Our proprietary post-CMOS wafer-scale process technology allows customers to build their devices using our die directly on a substrate, thereby enabling the development of products with the smallest form factors, while reducing cost and accelerating time to market.”
The MM8102 and MM8202 offer excellent frequency accuracy (lower than 300ppm for MM8102) and high frequency operation (up to 133MHz) — ideal for common high-bandwidth serial wireline interfaces. Both devices consume very low active power (2mA typical at 1.8V).
In addition, a stand-by mode is also supported where the power consumption is reduced to less than 1uA. The all-silicon, monolithic devices also offer excellent shock and vibration resistance as they generate frequencies electronically without any moving elements.
IDT offers easy-to-use evaluation boards to test the performance and functionality of its CMOS oscillators. The MM8202 and MM8102 devices are sampling now to qualified customers and are available in both wafer and industry-standard, crystal oscillator-compatible 5x3.2mm and 2.5x2.0mm packages, ranging in price from $0.52 to $0.59 for 1,000 units. Higher volume orders are offered at further discounts.
These ICs eliminate quartz-based resonators and oscillators in consumer, computation and storage applications with small form factor requirements and offer excellent link performance for all generations of common serial wireline interfaces, including S-ATA, PCIe, USB 2.0 and USB 3.0. The wafer form availability of the product enables chip-on-board (CoB) and multi-chip module (MCM) assembly designs for significant space savings.
The MM8202 and MM8102 are built on standard CMOS technology and do not require any mechanical frequency references, be it quartz or MEMS, offering IDT customers a fully integrated alternative to quartz-based resonators and oscillators. In addition, the MM8202 is ideal for thin profile consumer devices, such as high-capacity SIM cards and USB Flash drives.
“IDT is the first and only company to offer quartz-crystal-level performance with a CMOS oscillator in wafer form with high frequency accuracy,” said Michael McCorquodale, general manager of the IDT Silicon Frequency Control (SFC) business.
“Replacement of quartz crystals with our wire-bondable CMOS oscillator is a major breakthrough for form-factor-sensitive designs. It enables cost-effective CoB assembly for USB Flash drives, card readers and many other consumer applications. Our proprietary post-CMOS wafer-scale process technology allows customers to build their devices using our die directly on a substrate, thereby enabling the development of products with the smallest form factors, while reducing cost and accelerating time to market.”
The MM8102 and MM8202 offer excellent frequency accuracy (lower than 300ppm for MM8102) and high frequency operation (up to 133MHz) — ideal for common high-bandwidth serial wireline interfaces. Both devices consume very low active power (2mA typical at 1.8V).
In addition, a stand-by mode is also supported where the power consumption is reduced to less than 1uA. The all-silicon, monolithic devices also offer excellent shock and vibration resistance as they generate frequencies electronically without any moving elements.
IDT offers easy-to-use evaluation boards to test the performance and functionality of its CMOS oscillators. The MM8202 and MM8102 devices are sampling now to qualified customers and are available in both wafer and industry-standard, crystal oscillator-compatible 5x3.2mm and 2.5x2.0mm packages, ranging in price from $0.52 to $0.59 for 1,000 units. Higher volume orders are offered at further discounts.
AMD works with Microsoft, HP to raise bar for 2P price/performance with Windows Server 2008 R2
SUNNYVALE, USA: AMD has announced world-record 2P price/performance scores in the TPC-E and TPC-C benchmark tests for on-line transaction processing. The record-setting scores were achieved on an HP ProLiant DL385 G7 server powered by the new AMD Opteron 6000 Series platform.
“AMD, Microsoft and HP continue to work in tandem – from engineering to marketing – with the common goal of bringing efficiency and scalability to our joint enterprise computing customers,” said Nigel Dessau, senior vice president and chief marketing officer, AMD. “AMD is delivering optimized price/performance with the latest release of the AMD Opteron 6000 Series platform, while delivering technology solutions designed to address the variety of real-world computing demands our customers face every day.”
The following TPC-E and TPC-C benchmark scores were posted on April 8, 2010:
TPC-E: HP ProLiant DL385 G7 server powered by AMD Opteron processor Model 6176 SE running Microsoft SQL Server R2 and Microsoft Windows Server 2008 R2 achieved a score of $296.00 USD per tpsE.
TPC-C: HP ProLiant DL385 G7 server based on AMD Opteron processor Model 6176 SE running Microsoft SQL Server 2005 and Microsoft Windows Server 2008 R2 achieved a score of .60 USD per tpmC.
“Microsoft, AMD and HP are delivering compelling economic reasons for customers to move their databases onto the latest server and software platforms,” said David McCann, general manager, Windows Server Marketing at Microsoft.
“The latest TPC benchmark scores demonstrate how these solutions deliver outstanding price/performance, driving home the value that IT professionals can realize when upgrading from Microsoft Windows Server 2000 and Windows Server 2003, which will no longer be supported after this year.”
“Clients want scalable technology that can effectively handle data-intensive workloads such as online transaction processing,” said Dave Peterson, group manager of HP ProLiant product marketing, Industry Standard Servers, HP. “HP ProLiant G7 servers with the AMD Opteron 6000 Series platform provide the performance and return on investment required for these markets.”
Paired with the newly launched AMD Opteron 6000 series platform, Microsoft SQL Server 2008 R2 addresses the needs of database customers worldwide, enabling businesses to deliver near real-time information with the outstanding scalability and overall data center efficiency that’s needed to help businesses grow and remain flexible.
“AMD, Microsoft and HP continue to work in tandem – from engineering to marketing – with the common goal of bringing efficiency and scalability to our joint enterprise computing customers,” said Nigel Dessau, senior vice president and chief marketing officer, AMD. “AMD is delivering optimized price/performance with the latest release of the AMD Opteron 6000 Series platform, while delivering technology solutions designed to address the variety of real-world computing demands our customers face every day.”
The following TPC-E and TPC-C benchmark scores were posted on April 8, 2010:
TPC-E: HP ProLiant DL385 G7 server powered by AMD Opteron processor Model 6176 SE running Microsoft SQL Server R2 and Microsoft Windows Server 2008 R2 achieved a score of $296.00 USD per tpsE.
TPC-C: HP ProLiant DL385 G7 server based on AMD Opteron processor Model 6176 SE running Microsoft SQL Server 2005 and Microsoft Windows Server 2008 R2 achieved a score of .60 USD per tpmC.
“Microsoft, AMD and HP are delivering compelling economic reasons for customers to move their databases onto the latest server and software platforms,” said David McCann, general manager, Windows Server Marketing at Microsoft.
“The latest TPC benchmark scores demonstrate how these solutions deliver outstanding price/performance, driving home the value that IT professionals can realize when upgrading from Microsoft Windows Server 2000 and Windows Server 2003, which will no longer be supported after this year.”
“Clients want scalable technology that can effectively handle data-intensive workloads such as online transaction processing,” said Dave Peterson, group manager of HP ProLiant product marketing, Industry Standard Servers, HP. “HP ProLiant G7 servers with the AMD Opteron 6000 Series platform provide the performance and return on investment required for these markets.”
Paired with the newly launched AMD Opteron 6000 series platform, Microsoft SQL Server 2008 R2 addresses the needs of database customers worldwide, enabling businesses to deliver near real-time information with the outstanding scalability and overall data center efficiency that’s needed to help businesses grow and remain flexible.
Thursday, April 29, 2010
DALSA intros high resolution smart camera for single point machine vision inspection
BILLERICA, USA: DALSA Corp., a leader in machine vision technology, has announced the availability of a high resolution model of its BOA vision system, a highly integrated smart camera that comprises all of the elements of an industrial machine vision system. The new BOA M1280 offers superior image quality at a resolution of 1280 x 960 and operates at up to 24 frames per second.
“High resolution sensors provide greater measurement accuracy and are able to distinguish very small features that, if missed, could render a product defective,” says Steve Geraghty, director of DALSA Industrial Products. “High resolution imagery, combined with the processing capabilities of the BOA smart camera, offers manufacturers of all industries a very capable inspection solution at a very affordable price.”
DALSA’s BOA is an all-in-one machine vision solution that is smarter, easier to use, and more flexible than previous generations of smart cameras. It is the first smart camera in its class to incorporate multiple processing engines. This enables algorithm optimization via DSP, application management via CPU, and sensor management via FPGA.
It is also the first smart camera that offers truly embedded application software, which is easily set-up through a standard web browser. There is no software to install, and therefore no version control problems. BOA delivers greater flexibility for its users via a rugged, easy-to-mount enclosure, built-in factory communications, and a low deployment cost.
The monochrome version of the new high-resolution BOA vision system, Model M1280, is available immediately. A complementary color version will be available later in the year.
“High resolution sensors provide greater measurement accuracy and are able to distinguish very small features that, if missed, could render a product defective,” says Steve Geraghty, director of DALSA Industrial Products. “High resolution imagery, combined with the processing capabilities of the BOA smart camera, offers manufacturers of all industries a very capable inspection solution at a very affordable price.”
DALSA’s BOA is an all-in-one machine vision solution that is smarter, easier to use, and more flexible than previous generations of smart cameras. It is the first smart camera in its class to incorporate multiple processing engines. This enables algorithm optimization via DSP, application management via CPU, and sensor management via FPGA.
It is also the first smart camera that offers truly embedded application software, which is easily set-up through a standard web browser. There is no software to install, and therefore no version control problems. BOA delivers greater flexibility for its users via a rugged, easy-to-mount enclosure, built-in factory communications, and a low deployment cost.
The monochrome version of the new high-resolution BOA vision system, Model M1280, is available immediately. A complementary color version will be available later in the year.
Cadence reports Q1 2010 financial results
SAN JOSE, USA: Cadence Design Systems Inc. has announced results for the first quarter of fiscal year 2010.
Cadence reported first quarter 2010 revenue of $222 million, compared to revenue of $206 million reported for the same period in 2009. On a GAAP basis, Cadence recognized a net loss of $12 million, or $(0.04) per share on a diluted basis, in the first quarter of 2010, compared to a net loss of $63 million, or $(0.25) per share on a diluted basis in the same period in 2009.
Using Cadence's non-GAAP measure, net income in the first quarter of 2010 was $6 million, or $0.02 per share on a diluted basis, as compared to a net loss of $25 million, or $(0.10) per share on a diluted basis, in the same period in 2009.
“Cadence is off to a good start in 2010. The team executed across the board and our focus on customer engagement continues to yield success,” said Lip-Bu Tan, president and chief executive officer. “Business improved in all geographies with strength in Asia and North America, and in all platform areas, especially verification, custom and digital design.”
“We put up another consistent operating performance in the first quarter with our key operating metrics meeting or exceeding our expectations,” said Kevin S. Palatnik, senior vice president and chief financial officer.
In addition to using GAAP results to evaluate Cadence's business, management believes it is useful to measure results using a non-GAAP measure of net income or net loss, which excludes, as applicable, amortization of intangible assets, stock-based compensation expense, integration and acquisition-related costs, gains or losses and expenses or credits related to non-qualified deferred compensation plan assets, restructuring charges and credits, amortization of discount on convertible notes, equity in losses or income from investments, write-down of investments, and gains or losses on the sale of investments.
Non-GAAP net income or net loss is adjusted by the amount of additional taxes or tax benefit that the company would accrue if it used non-GAAP results instead of GAAP results to calculate the company's tax liability. See "GAAP to non-GAAP Reconciliation" below for further information on the non-GAAP measure.
The following statements are based on current expectations. These statements are forward-looking, and actual results may differ materially.
Business outlook
For the second quarter of 2010, the company expects total revenue in the range of $215 million to $225 million. Second quarter GAAP net loss per diluted share is expected to be in the range of $(0.05) to $(0.03). Net income per diluted share using the non-GAAP measure defined below is expected to be in the range of $0.02 to $0.04.
For the full year 2010, the company expects total revenue in the range of $865 million to $900 million. On a GAAP basis, net loss per diluted share for fiscal 2010 is expected to be in the range of $(0.23) to $(0.13). Using the non-GAAP measure defined below, net income per diluted share for fiscal 2010 is expected to be in the range of $0.05 to $0.15.
Cadence reported first quarter 2010 revenue of $222 million, compared to revenue of $206 million reported for the same period in 2009. On a GAAP basis, Cadence recognized a net loss of $12 million, or $(0.04) per share on a diluted basis, in the first quarter of 2010, compared to a net loss of $63 million, or $(0.25) per share on a diluted basis in the same period in 2009.
Using Cadence's non-GAAP measure, net income in the first quarter of 2010 was $6 million, or $0.02 per share on a diluted basis, as compared to a net loss of $25 million, or $(0.10) per share on a diluted basis, in the same period in 2009.
“Cadence is off to a good start in 2010. The team executed across the board and our focus on customer engagement continues to yield success,” said Lip-Bu Tan, president and chief executive officer. “Business improved in all geographies with strength in Asia and North America, and in all platform areas, especially verification, custom and digital design.”
“We put up another consistent operating performance in the first quarter with our key operating metrics meeting or exceeding our expectations,” said Kevin S. Palatnik, senior vice president and chief financial officer.
In addition to using GAAP results to evaluate Cadence's business, management believes it is useful to measure results using a non-GAAP measure of net income or net loss, which excludes, as applicable, amortization of intangible assets, stock-based compensation expense, integration and acquisition-related costs, gains or losses and expenses or credits related to non-qualified deferred compensation plan assets, restructuring charges and credits, amortization of discount on convertible notes, equity in losses or income from investments, write-down of investments, and gains or losses on the sale of investments.
Non-GAAP net income or net loss is adjusted by the amount of additional taxes or tax benefit that the company would accrue if it used non-GAAP results instead of GAAP results to calculate the company's tax liability. See "GAAP to non-GAAP Reconciliation" below for further information on the non-GAAP measure.
The following statements are based on current expectations. These statements are forward-looking, and actual results may differ materially.
Business outlook
For the second quarter of 2010, the company expects total revenue in the range of $215 million to $225 million. Second quarter GAAP net loss per diluted share is expected to be in the range of $(0.05) to $(0.03). Net income per diluted share using the non-GAAP measure defined below is expected to be in the range of $0.02 to $0.04.
For the full year 2010, the company expects total revenue in the range of $865 million to $900 million. On a GAAP basis, net loss per diluted share for fiscal 2010 is expected to be in the range of $(0.23) to $(0.13). Using the non-GAAP measure defined below, net income per diluted share for fiscal 2010 is expected to be in the range of $0.05 to $0.15.
Apple buys chip maker Intrinsity; to buy mobile-application developer Siri
USA: Well, if reports on the Internet are deemed to be true, Apple has again surprised everyone!
First, Apple is said to have bought Austin based chip design firm Intrinsity Inc. As per reports in The Statesman (USA), "Intrinsity designed key portions of Samsung Electronics Co. Ltd.'s low-power "Hummingbird" microprocessor, which was announced last year."
Also, Bloomberg has reported that Apple has also agreed to buy mobile-application developer Siri Inc. to "gain technology that lets users do Web searches from their phones by talking to them."
First, Apple is said to have bought Austin based chip design firm Intrinsity Inc. As per reports in The Statesman (USA), "Intrinsity designed key portions of Samsung Electronics Co. Ltd.'s low-power "Hummingbird" microprocessor, which was announced last year."
Also, Bloomberg has reported that Apple has also agreed to buy mobile-application developer Siri Inc. to "gain technology that lets users do Web searches from their phones by talking to them."
Intel to invest 2,300mn Pesos ($177 million) to expand Guadalajara design center
MEXICO CITY, MEXICO: During a press conference with Mexico President Felipe Calderon, Intel Corp. President and CEO Paul Otellini announced the company would invest 2,300 million pesos ($177 million) over three years to expand Intel's Guadalajara Design Center (GDC).
The investment will focus on increasing technology development activities, staffing and technology and education initiatives that support Calderon's National Digital Plan.
The Intel GDC focuses on the design, testing and validation of integrated circuits and other hardware, and education software technologies used in Intel products sold globally. The expansion will include the construction of a new building for technical labs, office space, a technology museum for children and an IT lab to support small- and medium-sized businesses. In addition, approximately 150 additional technical jobs will be created over the next 3 years, bringing the total number of GDC engineers to 550.
"As a global computing leader, we believe that investing in the future of discovery is an essential business decision," Otellini said. "Our team in Mexico will continue to help us do this. This new investment today extends our long-term commitment to Mexico. The highly technical work being done at our research center here has been extraordinary, and today we are taking it to a new level."
The new campus will adhere to world-class design and construction standards and to minimize its impact on the environment. For example, it will seek Leadership in Energy and Environmental Design (LEED) certification, which provides independent, third-party verification that a building meets the highest green building and performance measures.
The GDC is Intel's largest site in Mexico and where all its technology development activities in Mexico are based. Since it was established 10 years ago, it has grown from 33 employees to over 400 value-added jobs. In addition to technology development activities, the GDC also has several initiatives in place at local universities aimed at fostering the region's technical talent pool. Nearly 100 undergraduate students have participated in these programs in the past 18 months.
Additionally, to make possible the GDC's mission -- to "help to transform prototypes into products" and continue tackling current and future technologies -- the new site will increase its product validation activities. Validation is a critical part of Intel's product development cycle. Since its foundation, the GDC has contributed to the development of more than 40 leading processor and chipset products distributed around the world. The center aims to increase its technical contributions in the upcoming years.
With this investment, Intel also seeks to increase its contribution to the development of the national and local technological ecosystem. For example, more than 20 research and talent development projects have been completed or are underway with the university system. In addition, a multi-core technology lab has been set at the Information Technology Institute of Jalisco to help local small- and medium-sized businesses learn multi-core technologies that will be key for their competitiveness. Also, more than 50 interns spend six to 12 months in the GDC's labs learning about state-of-the-art technologies and engineering processes.
"Innovation results in the making of things, the solving of problems and improvements in society," said Jesus Palomino, general manager of the Guadalajara Design Center. "And, forward-looking government policies like the National Digital Plan, paired with investment in innovation, are at the center of economic growth. Today, Intel is reinforcing its commitment to technology development in Mexico and to supporting the government's plans to use technology to advance the country."
The investment will focus on increasing technology development activities, staffing and technology and education initiatives that support Calderon's National Digital Plan.
The Intel GDC focuses on the design, testing and validation of integrated circuits and other hardware, and education software technologies used in Intel products sold globally. The expansion will include the construction of a new building for technical labs, office space, a technology museum for children and an IT lab to support small- and medium-sized businesses. In addition, approximately 150 additional technical jobs will be created over the next 3 years, bringing the total number of GDC engineers to 550.
"As a global computing leader, we believe that investing in the future of discovery is an essential business decision," Otellini said. "Our team in Mexico will continue to help us do this. This new investment today extends our long-term commitment to Mexico. The highly technical work being done at our research center here has been extraordinary, and today we are taking it to a new level."
The new campus will adhere to world-class design and construction standards and to minimize its impact on the environment. For example, it will seek Leadership in Energy and Environmental Design (LEED) certification, which provides independent, third-party verification that a building meets the highest green building and performance measures.
The GDC is Intel's largest site in Mexico and where all its technology development activities in Mexico are based. Since it was established 10 years ago, it has grown from 33 employees to over 400 value-added jobs. In addition to technology development activities, the GDC also has several initiatives in place at local universities aimed at fostering the region's technical talent pool. Nearly 100 undergraduate students have participated in these programs in the past 18 months.
Additionally, to make possible the GDC's mission -- to "help to transform prototypes into products" and continue tackling current and future technologies -- the new site will increase its product validation activities. Validation is a critical part of Intel's product development cycle. Since its foundation, the GDC has contributed to the development of more than 40 leading processor and chipset products distributed around the world. The center aims to increase its technical contributions in the upcoming years.
With this investment, Intel also seeks to increase its contribution to the development of the national and local technological ecosystem. For example, more than 20 research and talent development projects have been completed or are underway with the university system. In addition, a multi-core technology lab has been set at the Information Technology Institute of Jalisco to help local small- and medium-sized businesses learn multi-core technologies that will be key for their competitiveness. Also, more than 50 interns spend six to 12 months in the GDC's labs learning about state-of-the-art technologies and engineering processes.
"Innovation results in the making of things, the solving of problems and improvements in society," said Jesus Palomino, general manager of the Guadalajara Design Center. "And, forward-looking government policies like the National Digital Plan, paired with investment in innovation, are at the center of economic growth. Today, Intel is reinforcing its commitment to technology development in Mexico and to supporting the government's plans to use technology to advance the country."
CebaFlex FPGA-based board-level protocol acceleration subsystems launched
ESC 2010; EATONTOWN & SAN JOSE, USA: CebaTech Inc., an innovative developer of advanced embedded system solutions, has launched its CebaFlex series of PCI Express-enabled subsystem boards that boost protocol processing performance in data networking and enterprise storage systems by up to 10X.
Executing critical application protocols in FPGA-based hardware with a streamlined path to very low cost implementation for high-volume applications, CebaFlex offloads the central processing unit (CPU), freeing up valuable CPU cycles, which can be used for higher value-add application processing. This offload significantly improves the system-level performance-to-cost ratio.
CebaFlex’s re-programmability enables OEM customers to rapidly deploy next-generation equipment, independent of the CPU technology lifecycle. Its in-system upgrade capability enables the after-market addition of new software functionality to the system, boosting performance, and enabling OEM customers to continuously address emerging market opportunities with speed and agility.
Enhancing data networking and storage application performance
CebaFlex addresses the missing link in the hardware realization of storage and data networking protocol stacks. The transport and link-level framing protocols have already benefited greatly from their migration to hardware implementations.
CebaFlex migrates the missing link – the data management layer - from slow and power-hungry CPU executed software, to FPGA-based hardware, achieving an order of magnitude improvement in performance at a fraction of the cost of developing a custom chip – and with the added advantage of being reprogrammable.
CebaFlex production-ready boards meet the tough reliability and environmental operating standards required by embedded systems equipment, and are used for both prototyping and product realization. The PCI Express interface enables plug ‘n’ play connection to standard network and storage chassis.
The initial CebaFlex offering supports industry-standard data management functions such as GZIP compression, GUNZIP decompression and AES encryption algorithms, using the company’s CebaRIP rapidly tunable intellectual property (IP) core library. CebaTech also implements custom protocols in CebaFlex subsystems as a full turnkey solution.
Making successful system-level-trade-offs
CebaFlex leverages its ANSI C-to-hardware compiler technology to design and tune hardware implementations of both standard and custom protocols to meet the different performance, power and area trade-offs required by different applications.
Using this technology, customers can have CebaTech compile and offload their ANSI C algorithms onto the hardware platform to produce a customized solution that meets their specific market needs.
The compiler technology’s high level of automation also enables the fast implementation of engineering change orders, even in the late stages of the design. OEMs can bring the right solution to market quickly, modify the trade-offs in response to changing end-customer requirements, and even cost-reduce it rapidly with a seamless ASIC-like conversion where product volumes and market timing make such a conversion viable.
“CebaFlex enables our customers to maximize their return on investment in three areas: designs-in-progress, deployed equipment, and next generation equipment. For designs-in-progress, customers can add CebaFlex to enhance performance without having to modify the existing design; for deployed equipment, they can upgrade performance in-system without incurring the expense of a chassis replacement,” said Ramana Jampala, CEO of CebaTech.
“Finally, they can deliver next generation equipment, independent of CPU roadmap constraints. Overall, customers can respond to changing market needs much more quickly.”
Executing critical application protocols in FPGA-based hardware with a streamlined path to very low cost implementation for high-volume applications, CebaFlex offloads the central processing unit (CPU), freeing up valuable CPU cycles, which can be used for higher value-add application processing. This offload significantly improves the system-level performance-to-cost ratio.
CebaFlex’s re-programmability enables OEM customers to rapidly deploy next-generation equipment, independent of the CPU technology lifecycle. Its in-system upgrade capability enables the after-market addition of new software functionality to the system, boosting performance, and enabling OEM customers to continuously address emerging market opportunities with speed and agility.
Enhancing data networking and storage application performance
CebaFlex addresses the missing link in the hardware realization of storage and data networking protocol stacks. The transport and link-level framing protocols have already benefited greatly from their migration to hardware implementations.
CebaFlex migrates the missing link – the data management layer - from slow and power-hungry CPU executed software, to FPGA-based hardware, achieving an order of magnitude improvement in performance at a fraction of the cost of developing a custom chip – and with the added advantage of being reprogrammable.
CebaFlex production-ready boards meet the tough reliability and environmental operating standards required by embedded systems equipment, and are used for both prototyping and product realization. The PCI Express interface enables plug ‘n’ play connection to standard network and storage chassis.
The initial CebaFlex offering supports industry-standard data management functions such as GZIP compression, GUNZIP decompression and AES encryption algorithms, using the company’s CebaRIP rapidly tunable intellectual property (IP) core library. CebaTech also implements custom protocols in CebaFlex subsystems as a full turnkey solution.
Making successful system-level-trade-offs
CebaFlex leverages its ANSI C-to-hardware compiler technology to design and tune hardware implementations of both standard and custom protocols to meet the different performance, power and area trade-offs required by different applications.
Using this technology, customers can have CebaTech compile and offload their ANSI C algorithms onto the hardware platform to produce a customized solution that meets their specific market needs.
The compiler technology’s high level of automation also enables the fast implementation of engineering change orders, even in the late stages of the design. OEMs can bring the right solution to market quickly, modify the trade-offs in response to changing end-customer requirements, and even cost-reduce it rapidly with a seamless ASIC-like conversion where product volumes and market timing make such a conversion viable.
“CebaFlex enables our customers to maximize their return on investment in three areas: designs-in-progress, deployed equipment, and next generation equipment. For designs-in-progress, customers can add CebaFlex to enhance performance without having to modify the existing design; for deployed equipment, they can upgrade performance in-system without incurring the expense of a chassis replacement,” said Ramana Jampala, CEO of CebaTech.
“Finally, they can deliver next generation equipment, independent of CPU roadmap constraints. Overall, customers can respond to changing market needs much more quickly.”
iPad and iPhone will credit to slight shortage on NAND Flash demand in 2H-10
TAIWAN: The iPad and the iPhone 4G, the new products of Apple, have attracted many spotlights this year. According to DRAMeXchange, 2010 iPhone shipment is expected to reach 40 million units while NAND Flash consumption will account 9 percent of total.
We believe that the NAND Flash demand will be boosted by Apple products, which will likely result in the mild shortage in 2H’10.
Given the delicate contents and support from telecom carriers, iPad and iPhone 4G are definitely the hottest products in 2010. We DRAMeXchange forecast 1H10 iPad shipment will likely be 1.7 million units while 7~8 million units will be targeted for 2010. Meanwhile, NAND Flash consumption of iPad will account around 3 percent of total NAND Flash consumption.
DRAMeXchange also indicates the prosperity of iPhone. In 2010, the total iPhone shipment will be up 60 percent to 40 million units from 25 million units in 2009 with the contribution of iPhone 4G. The new iPhone 4.0 O.S will be equipped with new functionalities such as multi-tasking, integrated E-mail service, series of enterprise applications and other minor improvements from previous O.S version.
From the past experience, Apple Inc. will double the storage capacity when new iPhone is launch besides the functionality and feature improvement, according to DRAMeXchange. The 64GB iPhone 4G will likely be launched this time.
iPad is equipped with multi-touched 9.7” LED color screen and will enhance the user experience and multi-media of iPod Touch. With the help from iTunes and Apple Apps store for downloading, Apple confirms its business model based on the digital content.
Besides, Apple Inc. will also introduce new e-book service,” iBooks”, with major American publishers to expand its territory to e-book market leverage with the color screen that iPad is equipped with. Despite the minor issue for WIFI iPad, we think that the iPad will show the great potential since Apple Apps and iPhone have done the great effort for iPad.
Besides WIFI version, 3G+WIFI iPad is announced to be launched at 4/30 that pricing at US$629/729/829 for 16GB/32GB/64GB respectively. AT&T will offer the 3G downloading service package that we DRAMeXchange think it will help to raise the consumer motivation.
Since new consumer electronics product such as iPod and iPhone always turn to the market hit with the strong shipment momentum, NAND Flash demand will be largely impact.
According to the FY2Q10 results that Apple released at 4/20, the iPhone shipment is record at 8.75 million units with 131 percent YoY growth rate besides the amazing profit figures. The iPhone market share in smartphone is sharply rocketing in past years that 2009 shipment is up 80 percent YoY to 25 million units.
DRAMeXchange indicates that iPhone shipment will continue its strong momentum given the great assistance from Apple Apps and open bungle package from various telecom carriers.
We believe that the NAND Flash demand will be boosted by Apple products, which will likely result in the mild shortage in 2H’10.
Given the delicate contents and support from telecom carriers, iPad and iPhone 4G are definitely the hottest products in 2010. We DRAMeXchange forecast 1H10 iPad shipment will likely be 1.7 million units while 7~8 million units will be targeted for 2010. Meanwhile, NAND Flash consumption of iPad will account around 3 percent of total NAND Flash consumption.
DRAMeXchange also indicates the prosperity of iPhone. In 2010, the total iPhone shipment will be up 60 percent to 40 million units from 25 million units in 2009 with the contribution of iPhone 4G. The new iPhone 4.0 O.S will be equipped with new functionalities such as multi-tasking, integrated E-mail service, series of enterprise applications and other minor improvements from previous O.S version.
From the past experience, Apple Inc. will double the storage capacity when new iPhone is launch besides the functionality and feature improvement, according to DRAMeXchange. The 64GB iPhone 4G will likely be launched this time.
iPad is equipped with multi-touched 9.7” LED color screen and will enhance the user experience and multi-media of iPod Touch. With the help from iTunes and Apple Apps store for downloading, Apple confirms its business model based on the digital content.
Besides, Apple Inc. will also introduce new e-book service,” iBooks”, with major American publishers to expand its territory to e-book market leverage with the color screen that iPad is equipped with. Despite the minor issue for WIFI iPad, we think that the iPad will show the great potential since Apple Apps and iPhone have done the great effort for iPad.
Besides WIFI version, 3G+WIFI iPad is announced to be launched at 4/30 that pricing at US$629/729/829 for 16GB/32GB/64GB respectively. AT&T will offer the 3G downloading service package that we DRAMeXchange think it will help to raise the consumer motivation.
Since new consumer electronics product such as iPod and iPhone always turn to the market hit with the strong shipment momentum, NAND Flash demand will be largely impact.
According to the FY2Q10 results that Apple released at 4/20, the iPhone shipment is record at 8.75 million units with 131 percent YoY growth rate besides the amazing profit figures. The iPhone market share in smartphone is sharply rocketing in past years that 2009 shipment is up 80 percent YoY to 25 million units.
DRAMeXchange indicates that iPhone shipment will continue its strong momentum given the great assistance from Apple Apps and open bungle package from various telecom carriers.
Atmel targets smart energy, building and home automation with BitCloud Profile Suite
ESC 2010; SAN JOSE, USA: Atmel Corp., a leader in MCU and touch solutions, announced the availability of Atmel BitCloud Profile Suite, a ready-to-use framework for rapid development of ZigBee-certified applications.
The suite includes a complete set of fully functional reference implementations of the ZigBee Application Profiles for ZigBee Smart Energy (ZSE), ZigBee Building Automation (ZBA) and ZigBee Home Automation (ZHA).
Atmel is also introducing the RZ600 evaluation kit, a tool accompanying BitCloud Profile Suite, and enables designers to prototype, develop and deploy ZigBee standards-compliant wireless applications for smart energy, home automation and building automation markets operating in both in 2.4GHz and the regional 700/800/900 MHz frequency bands.
The easy-to-use Atmel RZ600 development kit offers designers the flexibility to combine any Atmel RF transceiver with an Atmel microcontroller. The kit showcases Atmel's unique line-up of low power and high RF performance transceivers, which offer superior battery life for portable applications and extended range for robust connection.
When used with the free and certified BitCloud Profile Suite, RZ600 will help reduce system engineering design costs and slash time to market for a range of standards-compliant wireless products. RZ600 offers engineers the flexibility to design products for the 2.4 GHz IEEE 802.15.4-compliant markets including smart energy, building and home automation.
In addition to these markets, the Atmel transceivers enable designers to develop applications in the proprietary wireless application space for consumer products including toys, remote controls, walkie talkies and audio/video transfer applications.
"Atmel is committed to the growing ZigBee markets," said Magnus Pedersen, Product Marketing Director of MCU Wireless Solutions of Atmel. "By offering an easy-to-use development solution, designers can now have the flexibility to either design within the IEEE 802.15.4 standard or in proprietary wireless networks. We continue to offer solutions for the changing ZigBee markets."
The Atmel RZ600 includes radio extender boards, USB-to-10-pin-wireless dongles, and IEEE-802.15.4-compliant RF transceivers to support the worldwide 2.4GHz and the regional 700/800/900 MHz frequency bands. The Atmel BitCloud Profile Suite enables engineers to develop, debug and connect to wireless networks with radio extender boards that can be connected to Atmel evaluation boards.
These evaluation boards include the Atmel STK600 and the EVK1105 for wireless applications with an 8- or 32-bit AVR MCU and with the Atmel SAMx-EK wireless application development with an Atmel ARM-based MCU (with an ARM7 or Cortex core) and are combined with the latest ZSE 1.1 standard software.
The suite includes a complete set of fully functional reference implementations of the ZigBee Application Profiles for ZigBee Smart Energy (ZSE), ZigBee Building Automation (ZBA) and ZigBee Home Automation (ZHA).
Atmel is also introducing the RZ600 evaluation kit, a tool accompanying BitCloud Profile Suite, and enables designers to prototype, develop and deploy ZigBee standards-compliant wireless applications for smart energy, home automation and building automation markets operating in both in 2.4GHz and the regional 700/800/900 MHz frequency bands.
The easy-to-use Atmel RZ600 development kit offers designers the flexibility to combine any Atmel RF transceiver with an Atmel microcontroller. The kit showcases Atmel's unique line-up of low power and high RF performance transceivers, which offer superior battery life for portable applications and extended range for robust connection.
When used with the free and certified BitCloud Profile Suite, RZ600 will help reduce system engineering design costs and slash time to market for a range of standards-compliant wireless products. RZ600 offers engineers the flexibility to design products for the 2.4 GHz IEEE 802.15.4-compliant markets including smart energy, building and home automation.
In addition to these markets, the Atmel transceivers enable designers to develop applications in the proprietary wireless application space for consumer products including toys, remote controls, walkie talkies and audio/video transfer applications.
"Atmel is committed to the growing ZigBee markets," said Magnus Pedersen, Product Marketing Director of MCU Wireless Solutions of Atmel. "By offering an easy-to-use development solution, designers can now have the flexibility to either design within the IEEE 802.15.4 standard or in proprietary wireless networks. We continue to offer solutions for the changing ZigBee markets."
The Atmel RZ600 includes radio extender boards, USB-to-10-pin-wireless dongles, and IEEE-802.15.4-compliant RF transceivers to support the worldwide 2.4GHz and the regional 700/800/900 MHz frequency bands. The Atmel BitCloud Profile Suite enables engineers to develop, debug and connect to wireless networks with radio extender boards that can be connected to Atmel evaluation boards.
These evaluation boards include the Atmel STK600 and the EVK1105 for wireless applications with an 8- or 32-bit AVR MCU and with the Atmel SAMx-EK wireless application development with an Atmel ARM-based MCU (with an ARM7 or Cortex core) and are combined with the latest ZSE 1.1 standard software.
TI intros lowest power, high performance, JFET-input audio operational amplifiers
DALLAS, USA: Extending TI's Burr-Brown Audio line, Texas Instruments Inc. (TI) has introduced a family of JFET-input op amps featuring ultra-low noise and distortion to maximize audio system quality and performance.
With a quiescent current of 1.8 mA per channel, the OPA1641, OPA1642 and OPA1644 feature 40 percent lower power than the competition. The op amps support the multiple channels pro audio applications require, without increasing power consumption in high-performance audio circuits, such as broadcast studio equipment, analog and digital mixing consoles, and high-end A/V receivers.
Key features and benefits
* FET inputs deliver 40 percent lower input bias current (2 pA) than competitive devices, making the OPA1641, OPA1642 and OPA1644 better alternatives for applications requiring high source impedance.
* 15 percent lower noise (5 nV/root Hz) and distortion (0.00005% at 1 kHz) than the competition maintain excellent signal-to-noise ratio (SNR), even with high gain levels.
* Wide supply voltage range of +2.5 V to +18 V and rail-to-rail output swing allow for increased headroom, which is critical for audio analog-to-digital converter (ADC) front ends and digital-to-analog converter (DAC) post filters, including TI's PCM42xx and PCM17xx devices.
* 40 percent lower quiescent current (1.8 mA/channel) supports multiple channels without significant power consumption.
The single-channel OPA1641 is available today in a SO-8 package for $0.95 in 1,000-unit quantities. The two-channel OPA1642 is available in a SO-8 or MSOP-8 package for $1.45, and the four-channel OPA1644 can be purchased in a SO-14 or TSSOP-14 package for $1.95.
With a quiescent current of 1.8 mA per channel, the OPA1641, OPA1642 and OPA1644 feature 40 percent lower power than the competition. The op amps support the multiple channels pro audio applications require, without increasing power consumption in high-performance audio circuits, such as broadcast studio equipment, analog and digital mixing consoles, and high-end A/V receivers.
Key features and benefits
* FET inputs deliver 40 percent lower input bias current (2 pA) than competitive devices, making the OPA1641, OPA1642 and OPA1644 better alternatives for applications requiring high source impedance.
* 15 percent lower noise (5 nV/root Hz) and distortion (0.00005% at 1 kHz) than the competition maintain excellent signal-to-noise ratio (SNR), even with high gain levels.
* Wide supply voltage range of +2.5 V to +18 V and rail-to-rail output swing allow for increased headroom, which is critical for audio analog-to-digital converter (ADC) front ends and digital-to-analog converter (DAC) post filters, including TI's PCM42xx and PCM17xx devices.
* 40 percent lower quiescent current (1.8 mA/channel) supports multiple channels without significant power consumption.
The single-channel OPA1641 is available today in a SO-8 package for $0.95 in 1,000-unit quantities. The two-channel OPA1642 is available in a SO-8 or MSOP-8 package for $1.45, and the four-channel OPA1644 can be purchased in a SO-14 or TSSOP-14 package for $1.95.
Broadcom intros affordable Bluetooth handsfree car kit solution
IRVINE, USA: Broadcom Corp. has announced a new Bluetooth reference design platform that will enable improved audio quality and a more compelling user experience in a broader range of handsfree car kit devices.
This new design platform, built upon the successful Broadcom BCM20741 family of Bluetooth SoC solutions for headset devices, includes an upgrade to its SmartAudio sound and voice enhancement technology that reduces annoying background noise to deliver clear conversations in all driving conditions. Samsung has adopted this new platform for its HF1000 car kit device, which is now shipping.
Craig Ochikubo, Vice President & General Manager, Broadcom's Wireless Personal Area Networking line of business, said: "We continue to grow in the Bluetooth handsfree market by delivering a superior audio experience that provides key user benefits, and is friendly to the end-user and the environment. New car kit products based on our technology also benefit from the latest version of our popular SmartAudio technology with revolutionary noise suppression technologies optimized particularly for car kits."
This new design platform, built upon the successful Broadcom BCM20741 family of Bluetooth SoC solutions for headset devices, includes an upgrade to its SmartAudio sound and voice enhancement technology that reduces annoying background noise to deliver clear conversations in all driving conditions. Samsung has adopted this new platform for its HF1000 car kit device, which is now shipping.
Craig Ochikubo, Vice President & General Manager, Broadcom's Wireless Personal Area Networking line of business, said: "We continue to grow in the Bluetooth handsfree market by delivering a superior audio experience that provides key user benefits, and is friendly to the end-user and the environment. New car kit products based on our technology also benefit from the latest version of our popular SmartAudio technology with revolutionary noise suppression technologies optimized particularly for car kits."
Xilinx unveils ARM-based processing architecture for delivering unrivaled levels of performance in embedded systems
Embedded Systems Conference 2010; SAN JOSE, USA: Xilinx Inc. has introduced the architecture for a new Extensible Processing Platform that will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems.
The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing -- or any combination thereof -- needed to meet their application-specific requirements, including lower cost and power.
"Today's embedded software developer is being tasked to build complex applications that require tremendous levels of system performance, and they need to deliver that performance within tightly managed cost, schedule and power budgets," said Vin Ratford, Xilinx Senior Vice President for Worldwide Marketing and Business Development. "By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks."
A software-centric development flow is enabled by a processor-centric approach which presents a full processor system - including caches, memory controllers and commonly used connectivity and I/O peripherals - that boots and can run a variety of operating systems (OS) at power-up, such as Linux, Wind River's VxWorks and Micrium's uC-OSII.
The ARM architecture and its Connected Community ecosystem further maximize productivity for developers of embedded systems, while unrivaled performance is achieved by Xilinx's architecting the subsystem around ARM's dual-core Cortex-A9 MPCore processors, each running at up to 800 MHz, combined with the parallel-processing capabilities of Xilinx's high-performance, low-power 28-nanometer programmable logic.
The programmable logic is tightly coupled with the processor system through the high-bandwidth AMBA-AXI interconnects to accelerate key system functions by up to 100x, using off-the-shelf and/or custom IP. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O. It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration.
"Taking advantage of the parallelism of programmable logic is an excellent method for overcoming cost and power challenges in systems that require significant levels of high performance," said Simon Segars, President ARM Inc. "Xilinx's new architecture abstracts much of the hardware burden away from the embedded software developers' point of view, giving them an unprecedented level of control in the development process."
Software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries. Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM's RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.
Unrivaled performance to enable new applications
Demand for higher levels of embedded system performance is being driven by end market applications that require multifunctionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless.
In the automotive sector alone, with greater than 50 million cars produced each year, and an estimated 600 million motor vehicles on the road, today's $1.3-billion-dollar driver assistance market is expected to grow to $5.8 billion by in 2017 as manufacturers deploy more embedded systems in their vehicles to make them safer.
With statistics showing that 60 percent of front-end collisions could have been avoided with an extra .5-second response time, or that driver fatigue accounts for an estimated 30 percent of all driver fatalities, the motivation to leverage technology to save lives is clear. As developers of driver assistance systems pack more compute power into their applications, radar and infrared sensors, cameras and other system components must be installed into confined spaces within the automobile.
The new Xilinx Extensible Processing Platform offers a single-chip solution for optimizing application-specific hardware/software partitioning and accelerating functions in hardware to drive complex algorithms. This enables customers to further differentiate their embedded systems to gain a competitive advantage in their markets.
In a market expected to reach $46 billion by 2013(2), developers of new intelligent video technologies need processing platforms for building applications that can automatically monitor video patterns and body language, combined with audio, to make intelligent decisions and send alerts, thus reducing the chance for errors.
The technology is already moving to full high-definition video and frame rates up to 60 frames per second, but current solutions do not offer sufficient compute power for image processing and advanced analytic functions. The dual Cortex-A9MPCore-based processor system, coupled with the massive parallel-processing capabilities of the programmable logic, enables this capability. Developers also gain an opportunity for innovative algorithm design, scalability and field upgradability within a familiar ARM-based design environment.
Wireless telecommunication is being driven by the need for lower power, smaller physical form factors and reduced development costs, to support an ever-increasing number of users and data-hungry applications. New technologies such as 4G LTE (Long-Term Evolution) can address bandwidth requirements, but smaller, more efficient base stations are essential to meeting overall market requirements.
The Xilinx Extensible Processing Platform will help developers of next-generation wireless base stations to meet these needs by providing high-bandwidth parallel processing of 4G signals in combination with multiuser data management on Cortex A9 processors - all in a small, power-efficient, cost-effective integrated solution. Because the platform is extensible, developers have the flexibility to implement future equipment updates and performance upgrades of both hardware and software.
The new Extensible Processing Platform is part of Xilinx's Targeted Design Platform strategy, which provides customers with market- and application-specific environments that are easy to use, enabling them to evaluate and understand technology, and finally provide application platforms that can be modified and extended to accelerate their development time and focus on differentiation.
Xilinx has also engaged with ARM Services to provide detailed ARM Cortex-A9 hardware training for design teams and field application engineers who will be supporting the eventual product rollout.
The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing -- or any combination thereof -- needed to meet their application-specific requirements, including lower cost and power.
"Today's embedded software developer is being tasked to build complex applications that require tremendous levels of system performance, and they need to deliver that performance within tightly managed cost, schedule and power budgets," said Vin Ratford, Xilinx Senior Vice President for Worldwide Marketing and Business Development. "By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks."
A software-centric development flow is enabled by a processor-centric approach which presents a full processor system - including caches, memory controllers and commonly used connectivity and I/O peripherals - that boots and can run a variety of operating systems (OS) at power-up, such as Linux, Wind River's VxWorks and Micrium's uC-OSII.
The ARM architecture and its Connected Community ecosystem further maximize productivity for developers of embedded systems, while unrivaled performance is achieved by Xilinx's architecting the subsystem around ARM's dual-core Cortex-A9 MPCore processors, each running at up to 800 MHz, combined with the parallel-processing capabilities of Xilinx's high-performance, low-power 28-nanometer programmable logic.
The programmable logic is tightly coupled with the processor system through the high-bandwidth AMBA-AXI interconnects to accelerate key system functions by up to 100x, using off-the-shelf and/or custom IP. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O. It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration.
"Taking advantage of the parallelism of programmable logic is an excellent method for overcoming cost and power challenges in systems that require significant levels of high performance," said Simon Segars, President ARM Inc. "Xilinx's new architecture abstracts much of the hardware burden away from the embedded software developers' point of view, giving them an unprecedented level of control in the development process."
Software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries. Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM's RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.
Unrivaled performance to enable new applications
Demand for higher levels of embedded system performance is being driven by end market applications that require multifunctionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless.
In the automotive sector alone, with greater than 50 million cars produced each year, and an estimated 600 million motor vehicles on the road, today's $1.3-billion-dollar driver assistance market is expected to grow to $5.8 billion by in 2017 as manufacturers deploy more embedded systems in their vehicles to make them safer.
With statistics showing that 60 percent of front-end collisions could have been avoided with an extra .5-second response time, or that driver fatigue accounts for an estimated 30 percent of all driver fatalities, the motivation to leverage technology to save lives is clear. As developers of driver assistance systems pack more compute power into their applications, radar and infrared sensors, cameras and other system components must be installed into confined spaces within the automobile.
The new Xilinx Extensible Processing Platform offers a single-chip solution for optimizing application-specific hardware/software partitioning and accelerating functions in hardware to drive complex algorithms. This enables customers to further differentiate their embedded systems to gain a competitive advantage in their markets.
In a market expected to reach $46 billion by 2013(2), developers of new intelligent video technologies need processing platforms for building applications that can automatically monitor video patterns and body language, combined with audio, to make intelligent decisions and send alerts, thus reducing the chance for errors.
The technology is already moving to full high-definition video and frame rates up to 60 frames per second, but current solutions do not offer sufficient compute power for image processing and advanced analytic functions. The dual Cortex-A9MPCore-based processor system, coupled with the massive parallel-processing capabilities of the programmable logic, enables this capability. Developers also gain an opportunity for innovative algorithm design, scalability and field upgradability within a familiar ARM-based design environment.
Wireless telecommunication is being driven by the need for lower power, smaller physical form factors and reduced development costs, to support an ever-increasing number of users and data-hungry applications. New technologies such as 4G LTE (Long-Term Evolution) can address bandwidth requirements, but smaller, more efficient base stations are essential to meeting overall market requirements.
The Xilinx Extensible Processing Platform will help developers of next-generation wireless base stations to meet these needs by providing high-bandwidth parallel processing of 4G signals in combination with multiuser data management on Cortex A9 processors - all in a small, power-efficient, cost-effective integrated solution. Because the platform is extensible, developers have the flexibility to implement future equipment updates and performance upgrades of both hardware and software.
The new Extensible Processing Platform is part of Xilinx's Targeted Design Platform strategy, which provides customers with market- and application-specific environments that are easy to use, enabling them to evaluate and understand technology, and finally provide application platforms that can be modified and extended to accelerate their development time and focus on differentiation.
Xilinx has also engaged with ARM Services to provide detailed ARM Cortex-A9 hardware training for design teams and field application engineers who will be supporting the eventual product rollout.
SEMATECH reports synergistic advances in new materials and process innovation for emerging semiconductor devices
HSINCHU, TAIWAN: To continue the industry’s historical trend of performance scaling, SEMATECH experts reported on integrated approaches to CMOS logic and memory device technology and 3D TSV (through silicon via) manufacturing at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA) on April 26-28, 2010.
In a series of eight research papers, an international team of SEMATECH researchers addressed the various challenges and process solutions for extending advanced memory and logic technologies. The papers, selected from hundreds of submissions, outlined leading-edge research in areas such as high-k/metal gate (HKMG) materials, flash memory, and planar and non-planar CMOS technologies.
“The processes, materials, and device structures that will define next generations of CMOS and non-CMOS technologies, and how they function when combined as a module, is of critical importance to enhance functionality and performance in future generations of devices,” said Raj Jammy, vice president of advanced technologies. “The research that was presented at VLSI-TSA demonstrates SEMATECH’s leadership and innovative thinking in new materials, processes and concepts that enable CMOS scaling and pave the way for emerging technologies.”
In one potentially industry-changing technology, Sitaram Arkalgud, director of SEMATECH’s 3D interconnect program, described a via-mid approach to TSV technology on a 300mm platform. Arkalgud discussed process development, module integration and the overall manufacturability outlook for via–mid TSV, a front-end process which allows a reduction in the interconnect length as well as an increase in bandwidth between the stacked chips, resulting in lower power, higher performance, and increased device density.
Additionally, SEMATECH front end process technologists reported technical advances in the following areas:
* Exploring alternative high-k dielectrics to address challenges in gate-first and gate-last technology for the 28 nm node and beyond. SEMATECH reported a higher performance in a silicon germanium (SiGe) P-channel MOSFETs (pFET) when integrated into a dual channel single metal gate CMOS. In a gate-last approach, SEMATECH results showed a low temperature process that achieves the CMOS voltage target for both the N channel and the P channel suitable for 20 nm generation.
* Determining that the extremely high energy and spatial resolution of synchrotron X-ray photoemission spectroscopy (XPS) and extended X-ray absorption fine structure (EXAFS) techniques applied to advanced hafnium-based dielectric film systems have revealed subtle and significant chemical state and crystal phase transitions that give rise to the mechanisms responsible for improved device performance.
* Identifying vacuum ultraviolet (VuV) reflectivity as an in-line metrology solution for characterizing sub-nm Al2O3 and La2O3 capping layers on advanced high-k film stacks
* Exploring the promise of FinFETs as candidates for continuing transistor scaling, even though measuring these devices presents challenges, particularly for understanding the dielectric interface, since the Si body on these devices is not available for probing. By changing from a transistor to a gated diode, SEMATECH determined that this problem can be avoided and robust, meaningful measurements can be obtained.
* Conducting a thorough study of TANOS structures that highlighted differences in how the degradation of program, erase, and retention modes are dominated by different mechanisms
* Through a systematic evaluation of the thermal budget dependence of the structure and property of III-V MOSFETs, demonstrating reduced external resistance with laser anneals - a critical building block for scaling III-V MOSFETs
* Describing experimental observations of a strained SiGe quantum well (QW) pMOSFET, showing that it is a promising candidate for CMOS technology at 22 nm node and beyond
* Highlighting the necessity of biaxial strain engineering to boost the performance of FinFETs through reducing parasitic resistance as the industry scales past the 22 nm node
The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) is sponsored by the Institute of Electrical and Electronics Engineers, or IEEE, a leading professional association for the advancement of technology in association with Taiwan’s Industrial Technology Research Institute (ITRI). VLSI-TSA is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.
In a series of eight research papers, an international team of SEMATECH researchers addressed the various challenges and process solutions for extending advanced memory and logic technologies. The papers, selected from hundreds of submissions, outlined leading-edge research in areas such as high-k/metal gate (HKMG) materials, flash memory, and planar and non-planar CMOS technologies.
“The processes, materials, and device structures that will define next generations of CMOS and non-CMOS technologies, and how they function when combined as a module, is of critical importance to enhance functionality and performance in future generations of devices,” said Raj Jammy, vice president of advanced technologies. “The research that was presented at VLSI-TSA demonstrates SEMATECH’s leadership and innovative thinking in new materials, processes and concepts that enable CMOS scaling and pave the way for emerging technologies.”
In one potentially industry-changing technology, Sitaram Arkalgud, director of SEMATECH’s 3D interconnect program, described a via-mid approach to TSV technology on a 300mm platform. Arkalgud discussed process development, module integration and the overall manufacturability outlook for via–mid TSV, a front-end process which allows a reduction in the interconnect length as well as an increase in bandwidth between the stacked chips, resulting in lower power, higher performance, and increased device density.
Additionally, SEMATECH front end process technologists reported technical advances in the following areas:
* Exploring alternative high-k dielectrics to address challenges in gate-first and gate-last technology for the 28 nm node and beyond. SEMATECH reported a higher performance in a silicon germanium (SiGe) P-channel MOSFETs (pFET) when integrated into a dual channel single metal gate CMOS. In a gate-last approach, SEMATECH results showed a low temperature process that achieves the CMOS voltage target for both the N channel and the P channel suitable for 20 nm generation.
* Determining that the extremely high energy and spatial resolution of synchrotron X-ray photoemission spectroscopy (XPS) and extended X-ray absorption fine structure (EXAFS) techniques applied to advanced hafnium-based dielectric film systems have revealed subtle and significant chemical state and crystal phase transitions that give rise to the mechanisms responsible for improved device performance.
* Identifying vacuum ultraviolet (VuV) reflectivity as an in-line metrology solution for characterizing sub-nm Al2O3 and La2O3 capping layers on advanced high-k film stacks
* Exploring the promise of FinFETs as candidates for continuing transistor scaling, even though measuring these devices presents challenges, particularly for understanding the dielectric interface, since the Si body on these devices is not available for probing. By changing from a transistor to a gated diode, SEMATECH determined that this problem can be avoided and robust, meaningful measurements can be obtained.
* Conducting a thorough study of TANOS structures that highlighted differences in how the degradation of program, erase, and retention modes are dominated by different mechanisms
* Through a systematic evaluation of the thermal budget dependence of the structure and property of III-V MOSFETs, demonstrating reduced external resistance with laser anneals - a critical building block for scaling III-V MOSFETs
* Describing experimental observations of a strained SiGe quantum well (QW) pMOSFET, showing that it is a promising candidate for CMOS technology at 22 nm node and beyond
* Highlighting the necessity of biaxial strain engineering to boost the performance of FinFETs through reducing parasitic resistance as the industry scales past the 22 nm node
The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) is sponsored by the Institute of Electrical and Electronics Engineers, or IEEE, a leading professional association for the advancement of technology in association with Taiwan’s Industrial Technology Research Institute (ITRI). VLSI-TSA is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.
Nuvoton rounds out next-generation Pro-X CODEC/SLCC family
SAN JOSE, USA: Nuvoton Technology Corp., a leading worldwide provider of semiconductors for consumer and computing applications, announced the expansion of its next-generation Pro-X (PROgrammable Extended CODEC/SLCC) Series devices with the introduction of the N681622 Subscriber Line Control Circuit (SLCC).
Supporting one Foreign eXchange Station (FXS) ports, the N681522 operates seamlessly with Nuvoton's recently introduced single-channel and dual channel Pro-X CODEC/SLCC devices -- the N681386 for narrowband (8kHz) operation and N681387 for wideband (16kHz) operation, as well as the dual-channel the N682386 (narrowband) and N682387 (wideband).
In the past, these four devices required an external analog front-end (AFE) consisting of discrete devices. The N681622 now integrates all the AFE transistors needed for a single-channel FXS into one low-cost package.
The resulting chipsets can be implemented in a variety of FXS solutions: single- and dual-channel, narrowband and wideband. The N681386 and N681622, for example, can be used to implement a single narrowband FXS solution, while the N682387 and two N681622s can be designed into dual-wideband FXS solutions.
By integrating discrete AFE components, the N681622 reduces total component count of a design up to 30 percent which yields corresponding inventory savings for manufacturers and reliability improvements for end users.
Additionally, the board space used by AFE devices can be reduced by more than half, making far more compact solutions possible. Furthermore, the N681622's AFE implementation reduces the designs' power consumption in all states, including over 20 percent improvement in the On-Hook state.
The N681622 extends the Nuvoton Pro-X architecture's objective of distributing temperature gains evenly across the circuit design, ensuring that no "hot spots" develop within end-user systems. By keeping each Subscriber Line Feed Circuit (SLFC) channel in separate packages with individual heat sinks, Nuvoton provides engineers with more options to control temperature -- even in the most challenging environments.
"The N681622 builds on Nuvoton's unique, widely deployed Pro-X architecture with a more highly integrated, complementary CODEC/SLCC that dramatically reduces power consumption, component count and board space in a wide range of FXS applications," said Saleel Awsare, president, Nuvoton Technology Corp. America. "Furthermore, this new device maintains Nuvoton's industry-leading audio performance benchmarks that deliver superior voice quality."
Supporting one Foreign eXchange Station (FXS) ports, the N681522 operates seamlessly with Nuvoton's recently introduced single-channel and dual channel Pro-X CODEC/SLCC devices -- the N681386 for narrowband (8kHz) operation and N681387 for wideband (16kHz) operation, as well as the dual-channel the N682386 (narrowband) and N682387 (wideband).
In the past, these four devices required an external analog front-end (AFE) consisting of discrete devices. The N681622 now integrates all the AFE transistors needed for a single-channel FXS into one low-cost package.
The resulting chipsets can be implemented in a variety of FXS solutions: single- and dual-channel, narrowband and wideband. The N681386 and N681622, for example, can be used to implement a single narrowband FXS solution, while the N682387 and two N681622s can be designed into dual-wideband FXS solutions.
By integrating discrete AFE components, the N681622 reduces total component count of a design up to 30 percent which yields corresponding inventory savings for manufacturers and reliability improvements for end users.
Additionally, the board space used by AFE devices can be reduced by more than half, making far more compact solutions possible. Furthermore, the N681622's AFE implementation reduces the designs' power consumption in all states, including over 20 percent improvement in the On-Hook state.
The N681622 extends the Nuvoton Pro-X architecture's objective of distributing temperature gains evenly across the circuit design, ensuring that no "hot spots" develop within end-user systems. By keeping each Subscriber Line Feed Circuit (SLFC) channel in separate packages with individual heat sinks, Nuvoton provides engineers with more options to control temperature -- even in the most challenging environments.
"The N681622 builds on Nuvoton's unique, widely deployed Pro-X architecture with a more highly integrated, complementary CODEC/SLCC that dramatically reduces power consumption, component count and board space in a wide range of FXS applications," said Saleel Awsare, president, Nuvoton Technology Corp. America. "Furthermore, this new device maintains Nuvoton's industry-leading audio performance benchmarks that deliver superior voice quality."
Advantech joins eNsemble Multi-Core Alliance to drive performance leadership on multi-core ATCA blades
TAIPEI, TAIWAN: Advantech, a global manufacturer of telecom computing blades and multi-core network platforms, has become a member of the eNsemble Multi-Core Alliance, a premier industry organization founded to drive best-in-class innovations in multi-core parallel processing platforms and software development.
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
”Advantech has a long history of working with multi-core processors, and we are excited to continue our innovative leadership by joining the prestigious eNsemble Multi-Core Alliance,” said Eddie Lai, Director of Business Development for Advantech Network Computing Group. “By collaborating with other technology leaders, we aim to accelerate the adoption of ATCA-based multi-core blades and solutions.”
Advantech provides mission critical hardware to the world's leading telecom and networking equipment manufacturers. With an extensively deployed customer base, Advantech designs products for AdvancedTCA, AdvancedMC and MicroTCA. Advantech’s network platform team also shares the same core design base to engineer multi-core processor designs into tabletop, 1U and 2U platforms for the world's leading brands in network security.
”Advantech is a leading provider of high-performance ATCA blades for the telecommunications infrastructure, and we welcome Advantech as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
”Advantech has a long history of working with multi-core processors, and we are excited to continue our innovative leadership by joining the prestigious eNsemble Multi-Core Alliance,” said Eddie Lai, Director of Business Development for Advantech Network Computing Group. “By collaborating with other technology leaders, we aim to accelerate the adoption of ATCA-based multi-core blades and solutions.”
Advantech provides mission critical hardware to the world's leading telecom and networking equipment manufacturers. With an extensively deployed customer base, Advantech designs products for AdvancedTCA, AdvancedMC and MicroTCA. Advantech’s network platform team also shares the same core design base to engineer multi-core processor designs into tabletop, 1U and 2U platforms for the world's leading brands in network security.
”Advantech is a leading provider of high-performance ATCA blades for the telecommunications infrastructure, and we welcome Advantech as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
D2 Technologies joins eNsemble Multi-Core Alliance to drive IP communications software leadership for multi-core processors
SANTA BARBARA, USA: D2 Technologies, Inc., a leading provider of embedded IP communications software platforms, has become a member of the eNsemble Multi-Core Alliance, a premier industry organization founded to drive best-in-class innovations in multi-core parallel processing platforms and software development.
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
“We congratulate the eNsemble Multi-Core Alliance for setting out to bring together all the pieces that are needed for OEMs to develop and ship high-performance systems that take advantage of multi-core processors,” said Doug Makishima, chief operating officer of D2 Technologies.
D2’s innovative IP communications solutions are used by manufacturers in a variety of consumer, enterprise and carrier products, delivering features such as advanced presence-based and push-to-x control of circuit switched PSTN/cellular and VoIP calls, video chat/call, IM, presence, email, SMS, PBX, and more.
Its revolutionary presence-based user interface, mCUE, is built on top of a multi-identity, multi-session, multi-protocol engine, enabling flexible interoperability with multiple communications services such as enterprise IP PBXs and UC systems, and commercial IM and social networking services like GoogleTalk, Yahoo!, MSN, AIM and Skype.
“D2 is a leading provider of converged IP communications solutions, and we welcome D2 as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
“We congratulate the eNsemble Multi-Core Alliance for setting out to bring together all the pieces that are needed for OEMs to develop and ship high-performance systems that take advantage of multi-core processors,” said Doug Makishima, chief operating officer of D2 Technologies.
D2’s innovative IP communications solutions are used by manufacturers in a variety of consumer, enterprise and carrier products, delivering features such as advanced presence-based and push-to-x control of circuit switched PSTN/cellular and VoIP calls, video chat/call, IM, presence, email, SMS, PBX, and more.
Its revolutionary presence-based user interface, mCUE, is built on top of a multi-identity, multi-session, multi-protocol engine, enabling flexible interoperability with multiple communications services such as enterprise IP PBXs and UC systems, and commercial IM and social networking services like GoogleTalk, Yahoo!, MSN, AIM and Skype.
“D2 is a leading provider of converged IP communications solutions, and we welcome D2 as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
ST adopts Magwel's full-wave 3D product for advanced signal integrity analysis and visualization
SAN JOSE, USA: Magwel N.V. announced that STMicroelectronics has selected Magwel’s DevEM tool for use in design and verification of high speed I/O circuitry. This selection comes after extensive evaluation of DevEM on structures and circuits developed for their most advanced process nodes.
“ST designs some of the most advanced and high performance ICs in the world and all layers of the stack can affect performance,” said Philippe Galy, Manager of Advanced Library Design & Solutions in the Central CAD Design and Solution group at STMicroelectronics, Crolles-France.
“The Magwel product was able to comprehend the parasitic coupling between metal stack (BEOL) and semiconductor circuitry (FEOL) and provide accurate results that match silicon. With better extraction and simulation from Magwel, we will be able to optimize circuit performance and reduce the need to build test silicon.”
Magwel combines the world of EM and TCAD into a single and self-consistent analysis engine, while also offering the highest capacity of any full-wave 3D extractor in the industry.
“ST, like our other customers, is experiencing significant returns on investment,” said Dündar Dumlugöl, CEO of Magwel. “DevEM, along with our Power Transistor Modeling tool, offers customers an unparalleled 3D simulation and extraction accuracy that closely matches silicon and minimizes re-spins.”
“ST designs some of the most advanced and high performance ICs in the world and all layers of the stack can affect performance,” said Philippe Galy, Manager of Advanced Library Design & Solutions in the Central CAD Design and Solution group at STMicroelectronics, Crolles-France.
“The Magwel product was able to comprehend the parasitic coupling between metal stack (BEOL) and semiconductor circuitry (FEOL) and provide accurate results that match silicon. With better extraction and simulation from Magwel, we will be able to optimize circuit performance and reduce the need to build test silicon.”
Magwel combines the world of EM and TCAD into a single and self-consistent analysis engine, while also offering the highest capacity of any full-wave 3D extractor in the industry.
“ST, like our other customers, is experiencing significant returns on investment,” said Dündar Dumlugöl, CEO of Magwel. “DevEM, along with our Power Transistor Modeling tool, offers customers an unparalleled 3D simulation and extraction accuracy that closely matches silicon and minimizes re-spins.”
Infineon takes automotive semiconductor vendor top spot
BOSTON, USA: Long-term automotive semiconductor market leader Freescale has been displaced by its arch-rival Infineon, as revealed in the Strategy Analytics Automotive Electronics service report, “Automotive Semiconductor Market Shares 2009: Infineon Takes Top Spot from Freescale.”
As an early entrant, Freescale had enjoyed a significant lead over its nearest competitors since the outset of the automotive semiconductor market. However, the latest vendor rankings from Strategy Analytics shows that Infineon achieved $1.31 billion in CY 2009 automotive revenues (9 percent share) 2009 compared to Freescale at $1.163 billion (8 percent share).
In 2009, automotive semiconductor demand fell for an unprecedented second year in a row. Infineon’s total automotive revenues also fell in both years, but in each case Infineon fell to a lesser degree than Freescale.
Also, Freescale had the greatest exposure from the North American market – which suffered the greatest regional declines in 2008 and 2009. Finally, in 2009, Infineon found some very modest growth from the emerging economic regions, while Freescale’s emerging region revenues declined.
None of the automotive semiconductor vendors escaped unscathed from the drastic declines in automotive demand precipitated in the latter part of 2008, resulting in an average year-on-year company revenue decline of 22 percent. Compared to 2008, each of the top three vendors - Infineon, Freescale, and ST – actually lost market share to some degree.
According to Chris Webber, VP of the Strategy Analytics Global Automotive Practice: “The automotive semiconductor market virtually ground to a halt in the first quarter of 2009, as falling OEM demand was exacerbated by inventory destocking in the supply chain. The high resurgence in demand that ensued in the third and fourth quarters was too little, too late to avoid significant 2009 revenue declines for all semiconductor vendors.”
Looking forward, the outlook is much brighter. “Supplier restocking activity and a real recovery in OEM demand will ensure a return to growth for vendors in 2010. In the medium and longer term, further growth will be driven by increased electronics penetration, particularly because the industry needs to meet future vehicle environmental and safety requirements,” added Ian Riches, Director, Automotive Electronics Service.
As an early entrant, Freescale had enjoyed a significant lead over its nearest competitors since the outset of the automotive semiconductor market. However, the latest vendor rankings from Strategy Analytics shows that Infineon achieved $1.31 billion in CY 2009 automotive revenues (9 percent share) 2009 compared to Freescale at $1.163 billion (8 percent share).
In 2009, automotive semiconductor demand fell for an unprecedented second year in a row. Infineon’s total automotive revenues also fell in both years, but in each case Infineon fell to a lesser degree than Freescale.
Also, Freescale had the greatest exposure from the North American market – which suffered the greatest regional declines in 2008 and 2009. Finally, in 2009, Infineon found some very modest growth from the emerging economic regions, while Freescale’s emerging region revenues declined.
None of the automotive semiconductor vendors escaped unscathed from the drastic declines in automotive demand precipitated in the latter part of 2008, resulting in an average year-on-year company revenue decline of 22 percent. Compared to 2008, each of the top three vendors - Infineon, Freescale, and ST – actually lost market share to some degree.
According to Chris Webber, VP of the Strategy Analytics Global Automotive Practice: “The automotive semiconductor market virtually ground to a halt in the first quarter of 2009, as falling OEM demand was exacerbated by inventory destocking in the supply chain. The high resurgence in demand that ensued in the third and fourth quarters was too little, too late to avoid significant 2009 revenue declines for all semiconductor vendors.”
Looking forward, the outlook is much brighter. “Supplier restocking activity and a real recovery in OEM demand will ensure a return to growth for vendors in 2010. In the medium and longer term, further growth will be driven by increased electronics penetration, particularly because the industry needs to meet future vehicle environmental and safety requirements,” added Ian Riches, Director, Automotive Electronics Service.
Silicon Laboratories acquires Silicon Clocks and CMEMS technology
AUSTIN, USA: Silicon Laboratories Inc. has announced the acquisition of Silicon Valley-based Silicon Clocks, an early stage company creating innovative microelectromechanical system (MEMS) technology.
Silicon Clocks’ CMEMS (CMOS+MEMS) technology is aligned with Silicon Labs’ efforts to leverage its CMOS-based timing products into high-volume applications such as consumer electronics.
Silicon Clocks pioneered the development of a MEMS process technology that allows for the fabrication of MEMS resonators and other sensor structures directly on top of standard CMOS wafers. This approach will eliminate the need for boutique semiconductor processing and enables new levels of performance, integration, and size by eliminating the electrical parasitics and packaging issues associated with traditional solutions that co-package a standalone MEMS device and an IC.
“The Silicon Clocks team has created a very innovative MEMS technology that is designed to be compatible with standard CMOS mixed-signal ICs, enabling a new category of timing products that reduce system cost and optimize performance in a tiny footprint,” said Mark Downing, vice president of business development and corporate strategy for Silicon Laboratories.
“In addition, we believe this is a strategic technology platform uniquely capable of integrating several different MEMS with their associated CMOS circuitry on the same monolithic die.”
Silicon Clocks will augment Silicon Labs’ R&D team and bring 20 key patents to the company.
Silicon Clocks’ CMEMS (CMOS+MEMS) technology is aligned with Silicon Labs’ efforts to leverage its CMOS-based timing products into high-volume applications such as consumer electronics.
Silicon Clocks pioneered the development of a MEMS process technology that allows for the fabrication of MEMS resonators and other sensor structures directly on top of standard CMOS wafers. This approach will eliminate the need for boutique semiconductor processing and enables new levels of performance, integration, and size by eliminating the electrical parasitics and packaging issues associated with traditional solutions that co-package a standalone MEMS device and an IC.
“The Silicon Clocks team has created a very innovative MEMS technology that is designed to be compatible with standard CMOS mixed-signal ICs, enabling a new category of timing products that reduce system cost and optimize performance in a tiny footprint,” said Mark Downing, vice president of business development and corporate strategy for Silicon Laboratories.
“In addition, we believe this is a strategic technology platform uniquely capable of integrating several different MEMS with their associated CMOS circuitry on the same monolithic die.”
Silicon Clocks will augment Silicon Labs’ R&D team and bring 20 key patents to the company.
Wednesday, April 28, 2010
Abatron joins eNsemble Multi-Core Alliance to promote development tools for multi-core processors
ROTKREUZ, SWITZERLAND: Abatron AG has become a member of the eNsemble Multi-Core Alliance, a premier industry organization founded to drive best-in-class innovations in multi-core parallel processing platforms and software development.
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
”We are pleased to be a part of the eNsemble Multi-Core Alliance and to support continued innovations in multi-core processing platforms,” said Max Vock, President of Abatron AG.
Abatron AG offers full on-chip development support for multi-core processors. The BDI3000 high-speed JTAG debug interface and its associated applications for development support multi-core and multi threaded development and control of the high performance NetLogic Microsystems XLR® and XLS® processors. This enables customers to perform low-level hardware development, Linux kernel development, as well as in-circuit flash programming.
”Abatron provides tools that are important to the development of multi-core systems, and we welcome Abatron as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
As a founding member of the eNsemble Multi-Core Alliance, NetLogic Microsystems is committed to an open programming model for its family of market-leading multi-core, multi-threaded processors to allow the tighter coupling between networking software and the XLR, XLS and XLP multi-core processors.
This enables significant improvements in the application development efficiency of software code and overall system performance. In addition, this enables the development of new enhanced services and applications for next-generation Internet networks that are highly optimized for multi-core, multi-threaded processors.
Supported by a broad base of world-class hardware and software providers, the eNsemble Multi-Core Alliance serves as the foundation upon which original equipment manufacturers (OEMs) can more effectively and more efficiently develop high-performance networking equipment using industry-leading multi-core processors.
”We are pleased to be a part of the eNsemble Multi-Core Alliance and to support continued innovations in multi-core processing platforms,” said Max Vock, President of Abatron AG.
Abatron AG offers full on-chip development support for multi-core processors. The BDI3000 high-speed JTAG debug interface and its associated applications for development support multi-core and multi threaded development and control of the high performance NetLogic Microsystems XLR® and XLS® processors. This enables customers to perform low-level hardware development, Linux kernel development, as well as in-circuit flash programming.
”Abatron provides tools that are important to the development of multi-core systems, and we welcome Abatron as a valuable member of the eNsemble Multi-Core Alliance,” said Behrooz Abdi, executive vice president and general manager at NetLogic Microsystems, a founding member of the eNsemble Multi-Core Alliance.
“By having a community of technology innovators who are respective leaders in their areas of expertise, the Alliance creates a platform on which these developers can innovate to create new, breakthrough applications and solutions that can take full advantage of the superior performance and functionality of multi-core processors.”
As a founding member of the eNsemble Multi-Core Alliance, NetLogic Microsystems is committed to an open programming model for its family of market-leading multi-core, multi-threaded processors to allow the tighter coupling between networking software and the XLR, XLS and XLP multi-core processors.
This enables significant improvements in the application development efficiency of software code and overall system performance. In addition, this enables the development of new enhanced services and applications for next-generation Internet networks that are highly optimized for multi-core, multi-threaded processors.
Samsung ships industry’s first multi-chip package with PRAM chip for handsets
SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd has announced the industry’s first multi-chip package (MCP) with PRAM – for use in mobile handsets beginning later this quarter.
The 512 megabit Samsung PRAM in the MCP is backward compatible with 40 nanometer-class* NOR flash memory in both its hardware and software functionality, allowing mobile handset designers the convenience of having multi-chip packaging fully compatible with past stand-alone PRAM chip technology. PRAM is expected to be widely embraced by next year as the successor to NOR flash in consumer electronics designs, to become a major memory technology.
“Memories for portable consumer devices today are at a major turning point as mobile applications increasingly require more diverse memory technologies,” said Dong-soo Jun, executive vice president, Memory Sales and Marketing, Samsung Electronics.
“The launch of our PRAM in an advanced MCP solution for the replacement of 40nm-class and finer geometry NOR meets this need head-on. Our PRAM MCP will not only enable handset designers to utilize conventional platforms, but expedite the introduction of LPDDR2 DRAM and next-generation PRAM technology as the leading-edge basis for high-performance solutions,” he added.
PRAM, which stores data via the phase change characteristics of its base material, an alloy of germanium, antimony and titanium, provides three-times faster data storage performance per word than NOR chips. This new PRAM-packaged memory combines the nonvolatile nature of flash memory with the high-speed capability of DRAM.
Its simple cell structure makes designing MCP chips for handsets a faster and easier process, with the imminent use of 30nm-class and finer process node technology to overcome long-time design difficulties inherent in NOR flash technology.
As a replacement for NOR, PRAM can more easily accommodate the growing demand for high-speed, high-density nonvolatile memory in mobile phones and other mobile applications such as MP3 players, personal multimedia players and navigational devices.
Samsung is continuing its research and development into PRAM and other advanced memory chips to enable faster ‘write’ capabilities, a key feature in taking photo images, providing multimedia messaging and recording video clips to reduce the standby time in data storage. This high-speed write capability will be important in a diverse span of digital storage and consumer devices, such as solid state drives (SSDs) and HDTVs.
The 512 megabit Samsung PRAM in the MCP is backward compatible with 40 nanometer-class* NOR flash memory in both its hardware and software functionality, allowing mobile handset designers the convenience of having multi-chip packaging fully compatible with past stand-alone PRAM chip technology. PRAM is expected to be widely embraced by next year as the successor to NOR flash in consumer electronics designs, to become a major memory technology.
“Memories for portable consumer devices today are at a major turning point as mobile applications increasingly require more diverse memory technologies,” said Dong-soo Jun, executive vice president, Memory Sales and Marketing, Samsung Electronics.
“The launch of our PRAM in an advanced MCP solution for the replacement of 40nm-class and finer geometry NOR meets this need head-on. Our PRAM MCP will not only enable handset designers to utilize conventional platforms, but expedite the introduction of LPDDR2 DRAM and next-generation PRAM technology as the leading-edge basis for high-performance solutions,” he added.
PRAM, which stores data via the phase change characteristics of its base material, an alloy of germanium, antimony and titanium, provides three-times faster data storage performance per word than NOR chips. This new PRAM-packaged memory combines the nonvolatile nature of flash memory with the high-speed capability of DRAM.
Its simple cell structure makes designing MCP chips for handsets a faster and easier process, with the imminent use of 30nm-class and finer process node technology to overcome long-time design difficulties inherent in NOR flash technology.
As a replacement for NOR, PRAM can more easily accommodate the growing demand for high-speed, high-density nonvolatile memory in mobile phones and other mobile applications such as MP3 players, personal multimedia players and navigational devices.
Samsung is continuing its research and development into PRAM and other advanced memory chips to enable faster ‘write’ capabilities, a key feature in taking photo images, providing multimedia messaging and recording video clips to reduce the standby time in data storage. This high-speed write capability will be important in a diverse span of digital storage and consumer devices, such as solid state drives (SSDs) and HDTVs.
Parallel Engines launches world’s largest semiconductor-IP directory for FPGAs
CUPERTINO, USA: Parallel Engines Corp. has announced the public availability of www.FPGAIPDirectory.com, indexing over 17,000 IP blocks and FPGA devices.
Customers can search for Semiconductor-IP and retrieve IP Vendor datasheets, IP meta-information, and FPGA device configurations. Meta-information includes IP interfaces, LUT, BRAM, I/O and embedded IP resources, costs and packages.
Parallel Engines is the brainchild of George Janac, Electronic Design Automation pioneer, founder of Chip Estimate; High Level Design Systems, and startup investor. “FPGA design has long been served by a disaggregated IP supply chain,” said Janac.
“Our goal is to change that. We are integrating many elements to bring EDA and IP together for FPGA. With 28nm FPGA devices coming into production, designers will struggle even more with implementation methodology choices and cost effectiveness.”
Parallel Engines has aggregated over 4,000 Soft-IP blocks and Embedded Hard-IP from over 300 vendors along with Verification and Software IP. www.FPGAIPDirectory.com includes FPGA devices from Xilinx, Altera, Actel and Lattice Semiconductor. Customers can find information on both IP and devices. Subscription customers will be able to access data for pricing, configurations, AMBA, AXI, AHB, OCP, interfaces, I/O standards, packages, power, etc.
Parallel Engines is also announcing expansion of its beta program for its Platform Specification system, FpgaRFQ (standing for FPGA Request-for-Quote). This system allows the definition of a FPGA Platforms based on IP content. Platforms can then optimally fit into one or more FPGA devices. In its final release form, this system will enable designers to find the optimal FPGA parts providing cost, power, design guidance, and ASIC versus FPGA tradeoffs.
Next Generation design will be standards based. On-Chip Busses, in the form of Network-on-Chip or Fabric will connect ever larger IP based subsystems. “FPGA, in production or ASIC prototyping, is the ideal vehicle for this design style,” said Janac.
“The combination of FPGAIPDirectory, FpgaRFQ, Standards, with Network-on-Chip Planning (part of FpgaRFQ) brings everything into one place.” Designers will see reduced time to market and reduced risk, while minimizing costs. Today FPGAIPDirectory contains over 600 IPs with standard on-chip connectors.
The company plans to announce, and release, additional products over the next two months.
Customers can search for Semiconductor-IP and retrieve IP Vendor datasheets, IP meta-information, and FPGA device configurations. Meta-information includes IP interfaces, LUT, BRAM, I/O and embedded IP resources, costs and packages.
Parallel Engines is the brainchild of George Janac, Electronic Design Automation pioneer, founder of Chip Estimate; High Level Design Systems, and startup investor. “FPGA design has long been served by a disaggregated IP supply chain,” said Janac.
“Our goal is to change that. We are integrating many elements to bring EDA and IP together for FPGA. With 28nm FPGA devices coming into production, designers will struggle even more with implementation methodology choices and cost effectiveness.”
Parallel Engines has aggregated over 4,000 Soft-IP blocks and Embedded Hard-IP from over 300 vendors along with Verification and Software IP. www.FPGAIPDirectory.com includes FPGA devices from Xilinx, Altera, Actel and Lattice Semiconductor. Customers can find information on both IP and devices. Subscription customers will be able to access data for pricing, configurations, AMBA, AXI, AHB, OCP, interfaces, I/O standards, packages, power, etc.
Parallel Engines is also announcing expansion of its beta program for its Platform Specification system, FpgaRFQ (standing for FPGA Request-for-Quote). This system allows the definition of a FPGA Platforms based on IP content. Platforms can then optimally fit into one or more FPGA devices. In its final release form, this system will enable designers to find the optimal FPGA parts providing cost, power, design guidance, and ASIC versus FPGA tradeoffs.
Next Generation design will be standards based. On-Chip Busses, in the form of Network-on-Chip or Fabric will connect ever larger IP based subsystems. “FPGA, in production or ASIC prototyping, is the ideal vehicle for this design style,” said Janac.
“The combination of FPGAIPDirectory, FpgaRFQ, Standards, with Network-on-Chip Planning (part of FpgaRFQ) brings everything into one place.” Designers will see reduced time to market and reduced risk, while minimizing costs. Today FPGAIPDirectory contains over 600 IPs with standard on-chip connectors.
The company plans to announce, and release, additional products over the next two months.
Synopsys universal DDR controllers improve performance, reduce cost of embedded DRAM interfaces
MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of the high-performance DesignWare® Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards.
The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys’ previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs.
The DesignWare Universal Protocol Controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133 Mbps, the maximum data rate of the DDR3 standard, and offer a broadly utilized DFI 2.1-compliant interface to the DDR PHY.
Furthermore, the Universal DDR Memory and Protocol Controllers enable designers to easily integrate multiple DDR interfaces into one design servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive with less risk and improved time-to-market.
The multi-port DesignWare Universal DDR Memory Controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. In addition, the DesignWare Universal DDR Memory Controller provides high memory bandwidth utilization through transaction reordering, bandwidth allocation per port, and quality-of-service (QoS) based arbitration for latency-sensitive and/or high-bandwidth traffic.
Complementing the DesignWare DDR Universal Memory Controller, the unique single-port DesignWare Universal DDR Protocol Controller is designed to optimize memory channel bandwidth utilization with reduced latency, allowing designers to implement a custom memory scheduler that is optimized for specific DRAM traffic patterns.
The DesignWare Universal DDR Protocol Controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in high-speed, general purpose process technologies and ease of timing closure in low power process technologies.
“As a fabless semiconductor company that pushes the limits of general purpose multicore processing to the highest performance per watt per silicon area, we need an established IP vendor that would enable us to optimize the throughput and latency of high-end DDR memory solutions” said Peleg Aviely, CTO at Plurality Ltd.
“After evaluating different IP vendors, we selected Synopsys based on their track record of delivering high-quality, silicon-proven DesignWare DDR IP solutions that are backed by a knowledgeable technical support team.”
“As DDR SDRAM standards continue to proliferate, it is vital to provide designers with a DDR IP solution that can support the breadth of SDRAM options,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The new DesignWare Universal DDR protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimizing the utilization of the memory channel bandwidth.”
The DesignWare Universal DDR protocol and memory controllers are part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.
The DesignWare Universal DDR protocol and memory controllers as well as the complementary PHYs are available now.
The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys’ previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs.
The DesignWare Universal Protocol Controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133 Mbps, the maximum data rate of the DDR3 standard, and offer a broadly utilized DFI 2.1-compliant interface to the DDR PHY.
Furthermore, the Universal DDR Memory and Protocol Controllers enable designers to easily integrate multiple DDR interfaces into one design servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive with less risk and improved time-to-market.
The multi-port DesignWare Universal DDR Memory Controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. In addition, the DesignWare Universal DDR Memory Controller provides high memory bandwidth utilization through transaction reordering, bandwidth allocation per port, and quality-of-service (QoS) based arbitration for latency-sensitive and/or high-bandwidth traffic.
Complementing the DesignWare DDR Universal Memory Controller, the unique single-port DesignWare Universal DDR Protocol Controller is designed to optimize memory channel bandwidth utilization with reduced latency, allowing designers to implement a custom memory scheduler that is optimized for specific DRAM traffic patterns.
The DesignWare Universal DDR Protocol Controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in high-speed, general purpose process technologies and ease of timing closure in low power process technologies.
“As a fabless semiconductor company that pushes the limits of general purpose multicore processing to the highest performance per watt per silicon area, we need an established IP vendor that would enable us to optimize the throughput and latency of high-end DDR memory solutions” said Peleg Aviely, CTO at Plurality Ltd.
“After evaluating different IP vendors, we selected Synopsys based on their track record of delivering high-quality, silicon-proven DesignWare DDR IP solutions that are backed by a knowledgeable technical support team.”
“As DDR SDRAM standards continue to proliferate, it is vital to provide designers with a DDR IP solution that can support the breadth of SDRAM options,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The new DesignWare Universal DDR protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimizing the utilization of the memory channel bandwidth.”
The DesignWare Universal DDR protocol and memory controllers are part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.
The DesignWare Universal DDR protocol and memory controllers as well as the complementary PHYs are available now.
Cadence issues blueprint to battle 'profitability gap'; counters semiconductor industry’s greatest threat
BANGAALORE, INDIA: Cadence Design Systems Inc. has laid out a new vision for the semiconductor industry, EDA360.
In outlining an application-driven approach to system design and development, Cadence issued a challenge to the semiconductor and electronic design automation (EDA) communities to address the growing “profitability gap” that threatens the vitality of the electronics industry.
According to the EDA360 vision, released during an event at The Tech Museum in San Jose, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it must change in order to continue as a successful, independent market. Without this change, EDA will struggle to solve the increasingly complex problems customers are facing now and in the future.
To download a full copy of the EDA360 vision paper visit http://www.eda360.com.
The need for change
Despite staggering consumer demand for advanced mobile computing devices and other compelling electronics devices, development practices are choking the innovation today’s technology makes possible. In a traditional disaggregated development approach, hardware is developed first and the operating system (OS) and applications are added later. While the hardware and OS are fully integrated, applications are confined to the underlying hardware/software platforms.
In addition, established electronics companies are increasingly being challenged by game-changing new entrants that focus their innovation and differentiation on applications or “apps.” These new entrants are now requiring semiconductor providers to supply “application-ready” platforms with hardware and software for a given application such as mobile computing.
Directly addressing this shift in the ecosystem, EDA360 outlines an application-driven development model where hardware is designed and developed to dynamically meet the needs of the application.
"As founder of an organization that is transforming the economics and technology of an industry so that we can improve opportunity for millions, I am constantly watching what others are doing,” said Nicholas Negroponte, founder and chairman, One Laptop per Child.
“Cadence has a vision and model with the potential to transform the economics and performance of the microprocessor industry and, by extension, devices every consumer takes for granted. The EDA360 manifesto outlines a vision that bears watching.”
Action Now: Cadence intros expanded collaboration, new products in support of EDA360
In support of this industry vision, Cadence also announced its initial actions to bring EDA360 to life – an expanded technical collaboration and new product family that will enable the adoption of this approach in the design and development of new, innovative electronic devices. These actions include:
Ecosystem approach to system realization
Because application-driven system design will enable customers to address extremely complex and difficult tasks, no one company can provide all the tools needed to fully integrate a system’s hardware and software elements.
A key tenet of the EDA360 vision is the need for an ecosystem that works to the benefit and profit of customers facing the challenges of today and tomorrow’s market imperatives.
As an initial step targeted at delivering on the promise of “system realization” in EDA360 terms, Cadence and Wind River announced a technical collaboration that aims to integrate the Cadence Incisive Software Extensions and Wind River’s Simics virtual platform.
This joint approach is expected to allow engineers to develop electronic designs on a virtual platform well in advance of hardware availability and improves the productivity of system engineers with planning, management, stimulus, checking and monitoring of unique hardware/software use cases. This level of cooperation is essential for improving system-level schedule predictability while reducing risk, and marks the first of many upcoming collaborative ventures in the Cadence system realization ecosystem.
“The electronics industry needs to adapt if it is to continue the tremendous innovations it has brought over the past 30 years,” said Vincent Rerolle, general manager of the Simics Division and chief strategy officer at Wind River.
“A collaborative ecosystem approach, that allows design teams to pick and choose the components best suited for their specific needs, is a necessary requirement in enabling open, standards-based solutions that can address costs and maximize profits. The integration of Cadence’s systems-based offerings with Simics provides a true virtual platform for all aspects of system development.”
Cadence verification computing platform
On Monday, the company announced the industry’s first fully integrated, high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment.
Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better quality embedded systems in a shorter time.
Cadence Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.
The Palladium XP verification computing platform provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better quality IP, subsystems, SoCs and systems.
Design teams can “hot swap” simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.
“Today, semiconductor companies need to excel at both hardware and software and those that are not able to expand beyond traditional, Moore’s Law-driven innovation will be significantly impacted,” said Lip-Bu Tan, president and CEO, Cadence.
“EDA360 is a call to action for the entire industry. Our customers are facing unfamiliar, extremely complex challenges and we must collaborate to deliver the advanced technology and solutions that enable success. In response, Cadence will execute an EDA360 strategy based on deep customer partnerships that solve the hard problems challenging our industry.”
In outlining an application-driven approach to system design and development, Cadence issued a challenge to the semiconductor and electronic design automation (EDA) communities to address the growing “profitability gap” that threatens the vitality of the electronics industry.
According to the EDA360 vision, released during an event at The Tech Museum in San Jose, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it must change in order to continue as a successful, independent market. Without this change, EDA will struggle to solve the increasingly complex problems customers are facing now and in the future.
To download a full copy of the EDA360 vision paper visit http://www.eda360.com.
The need for change
Despite staggering consumer demand for advanced mobile computing devices and other compelling electronics devices, development practices are choking the innovation today’s technology makes possible. In a traditional disaggregated development approach, hardware is developed first and the operating system (OS) and applications are added later. While the hardware and OS are fully integrated, applications are confined to the underlying hardware/software platforms.
In addition, established electronics companies are increasingly being challenged by game-changing new entrants that focus their innovation and differentiation on applications or “apps.” These new entrants are now requiring semiconductor providers to supply “application-ready” platforms with hardware and software for a given application such as mobile computing.
Directly addressing this shift in the ecosystem, EDA360 outlines an application-driven development model where hardware is designed and developed to dynamically meet the needs of the application.
"As founder of an organization that is transforming the economics and technology of an industry so that we can improve opportunity for millions, I am constantly watching what others are doing,” said Nicholas Negroponte, founder and chairman, One Laptop per Child.
“Cadence has a vision and model with the potential to transform the economics and performance of the microprocessor industry and, by extension, devices every consumer takes for granted. The EDA360 manifesto outlines a vision that bears watching.”
Action Now: Cadence intros expanded collaboration, new products in support of EDA360
In support of this industry vision, Cadence also announced its initial actions to bring EDA360 to life – an expanded technical collaboration and new product family that will enable the adoption of this approach in the design and development of new, innovative electronic devices. These actions include:
Ecosystem approach to system realization
Because application-driven system design will enable customers to address extremely complex and difficult tasks, no one company can provide all the tools needed to fully integrate a system’s hardware and software elements.
A key tenet of the EDA360 vision is the need for an ecosystem that works to the benefit and profit of customers facing the challenges of today and tomorrow’s market imperatives.
As an initial step targeted at delivering on the promise of “system realization” in EDA360 terms, Cadence and Wind River announced a technical collaboration that aims to integrate the Cadence Incisive Software Extensions and Wind River’s Simics virtual platform.
This joint approach is expected to allow engineers to develop electronic designs on a virtual platform well in advance of hardware availability and improves the productivity of system engineers with planning, management, stimulus, checking and monitoring of unique hardware/software use cases. This level of cooperation is essential for improving system-level schedule predictability while reducing risk, and marks the first of many upcoming collaborative ventures in the Cadence system realization ecosystem.
“The electronics industry needs to adapt if it is to continue the tremendous innovations it has brought over the past 30 years,” said Vincent Rerolle, general manager of the Simics Division and chief strategy officer at Wind River.
“A collaborative ecosystem approach, that allows design teams to pick and choose the components best suited for their specific needs, is a necessary requirement in enabling open, standards-based solutions that can address costs and maximize profits. The integration of Cadence’s systems-based offerings with Simics provides a true virtual platform for all aspects of system development.”
Cadence verification computing platform
On Monday, the company announced the industry’s first fully integrated, high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment.
Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better quality embedded systems in a shorter time.
Cadence Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.
The Palladium XP verification computing platform provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better quality IP, subsystems, SoCs and systems.
Design teams can “hot swap” simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.
“Today, semiconductor companies need to excel at both hardware and software and those that are not able to expand beyond traditional, Moore’s Law-driven innovation will be significantly impacted,” said Lip-Bu Tan, president and CEO, Cadence.
“EDA360 is a call to action for the entire industry. Our customers are facing unfamiliar, extremely complex challenges and we must collaborate to deliver the advanced technology and solutions that enable success. In response, Cadence will execute an EDA360 strategy based on deep customer partnerships that solve the hard problems challenging our industry.”
TI embraces Linux for C64x DSPs
SAN JOSE, USA: Texas Instruments Inc. (TI) announced Linux kernel support for its TMS320C64x digital signal processors (DSPs) and multicore system-on-chips (SoCs) targeted for applications such as communications and mission critical infrastructure, medical diagnostics, and high-performance test and measurement.
As customers move towards open source as a key element of their products, application developers can benefit from the availability of Linux on TI's high-performance DSPs by having less software to develop, and focusing more on differentiating features and software in their applications.
"TI's C64x processors have an enviable footprint in signal processing oriented high-performance multicore applications," said Olaf Soentgen of Nash Technologies. "The introduction of Linux support expands the utility of the C64x into portions of these applications that traditionally have been reserved for RISC cores. We are taking advantage of Linux availability on TI's SoC to lower the cost and simplify the development of femtocell base stations."
TI's C64x Linux effort is a community collaboration with considerable support already in place. As part of the effort to port the Linux kernel to the C64x ISA, Code Sourcery is developing a complete tool chain including support for the GNU Compiler Collection (GCC) and the GNU Project Debugger (GDB).
The project's goal is that both the C64x Linux kernel and the GCC/GDB tools will be accepted by kernel.org and the Free Software Foundation, making both fully supported as open source community projects. In addition, TI will sponsor a Linux-C64x portal and a community-oriented distribution program to facilitate communication and development around this technology.
ENEA is making its open source, scalable multicore communications stack available to the C64x Linux community, as well as offering advanced multicore platform software and debugging tools. Nash Technologies is implementing features ranging from advanced chip level functions, such as multicore interprocessor communications, to complete LTE protocols. PolyCore Software, also an early community participant, is implementing the MCAPI multicore communications framework.
"Our customers are rapidly moving towards open source as a critical element of their solutions," said Brian Glinsman, general manager of TI's communications infrastructure business.
"Because of the C64x-based products' ultra low power consumption and cost effectiveness, customers are interested in running traditional DSP MAC/PHY and codec algorithms as well as classic RISC control code and protocols on our DSPs. TI's embracing of Linux and an open tool chain for the industry workhorse C64x makes this kind of integration practical."
Product support for the C64x Linux kernel will be available for TI's TMS320C6472, TMS320C6474, TMS320C6455 and TMS320C6457 devices in 3Q10.
As customers move towards open source as a key element of their products, application developers can benefit from the availability of Linux on TI's high-performance DSPs by having less software to develop, and focusing more on differentiating features and software in their applications.
"TI's C64x processors have an enviable footprint in signal processing oriented high-performance multicore applications," said Olaf Soentgen of Nash Technologies. "The introduction of Linux support expands the utility of the C64x into portions of these applications that traditionally have been reserved for RISC cores. We are taking advantage of Linux availability on TI's SoC to lower the cost and simplify the development of femtocell base stations."
TI's C64x Linux effort is a community collaboration with considerable support already in place. As part of the effort to port the Linux kernel to the C64x ISA, Code Sourcery is developing a complete tool chain including support for the GNU Compiler Collection (GCC) and the GNU Project Debugger (GDB).
The project's goal is that both the C64x Linux kernel and the GCC/GDB tools will be accepted by kernel.org and the Free Software Foundation, making both fully supported as open source community projects. In addition, TI will sponsor a Linux-C64x portal and a community-oriented distribution program to facilitate communication and development around this technology.
ENEA is making its open source, scalable multicore communications stack available to the C64x Linux community, as well as offering advanced multicore platform software and debugging tools. Nash Technologies is implementing features ranging from advanced chip level functions, such as multicore interprocessor communications, to complete LTE protocols. PolyCore Software, also an early community participant, is implementing the MCAPI multicore communications framework.
"Our customers are rapidly moving towards open source as a critical element of their solutions," said Brian Glinsman, general manager of TI's communications infrastructure business.
"Because of the C64x-based products' ultra low power consumption and cost effectiveness, customers are interested in running traditional DSP MAC/PHY and codec algorithms as well as classic RISC control code and protocols on our DSPs. TI's embracing of Linux and an open tool chain for the industry workhorse C64x makes this kind of integration practical."
Product support for the C64x Linux kernel will be available for TI's TMS320C6472, TMS320C6474, TMS320C6455 and TMS320C6457 devices in 3Q10.
Atmel maXTouch solution enables touchscreen innovation for Samsung’s AMOLED Wave smartphone
SAN JOSE, USA: Atmel Corp. a leader in microcontroller and touch technology solutions, announced that its maXTouch controller powers the touchscreen
interface in the recently announced Samsung Wave smartphone.
Released during Mobile World Congress in Barcelona, the Wave S8500 boasts a 3.3-inch Super AMOLED touchscreen that integrates Atmel’s maXTouch capacitive touchscreen technology to make the user interface incredibly responsive and intuitive. The Samsung Wave also includes a 5-megapixel camera with auto focus and support for 720p HD video recording and playback.
"The Atmel maXTouch capacitive touchscreen technology has enabled the Samsung engineering team to quickly and easily design leading-edge touchscreen capabilities into the Wave to help deliver an unrivaled user experience on a smartphone. Access to development tools and engineering support helped Samsung quickly deliver new levels of performance and unique touchscreen features,” said Kim, DongSub, Principal Engineer Visual Lab, Mobile Communication Division of Telecommunication Business at Samsung.
The announcement of the Samsung Wave smartphone has generated positive reviews. According to the editorial team at Think Digit On-line Electronics Review, “The mobile giant has revealed a touch smartphone that is excellent in both looks and design, with a metallic finish and thin-sculpted profile. The phone's 3.3-inch super-AMOLED touchscreen is large and looks good.”
“Atmel’s maXTouch solutions provide unlimited capacitive touch capabilities, great linearity and advanced touch screen functionality,” said Chris Ard, Senior Director of Touch Marketing, Atmel.
“These solutions also support the touch of a finger, stylus and even touches from a user with gloves on. The rapid response time and rejection of unintended touches enable Samsung to create the most powerful and intuitive user interfaces for their new product developments, such as the Wave.”
interface in the recently announced Samsung Wave smartphone.
Released during Mobile World Congress in Barcelona, the Wave S8500 boasts a 3.3-inch Super AMOLED touchscreen that integrates Atmel’s maXTouch capacitive touchscreen technology to make the user interface incredibly responsive and intuitive. The Samsung Wave also includes a 5-megapixel camera with auto focus and support for 720p HD video recording and playback.
"The Atmel maXTouch capacitive touchscreen technology has enabled the Samsung engineering team to quickly and easily design leading-edge touchscreen capabilities into the Wave to help deliver an unrivaled user experience on a smartphone. Access to development tools and engineering support helped Samsung quickly deliver new levels of performance and unique touchscreen features,” said Kim, DongSub, Principal Engineer Visual Lab, Mobile Communication Division of Telecommunication Business at Samsung.
The announcement of the Samsung Wave smartphone has generated positive reviews. According to the editorial team at Think Digit On-line Electronics Review, “The mobile giant has revealed a touch smartphone that is excellent in both looks and design, with a metallic finish and thin-sculpted profile. The phone's 3.3-inch super-AMOLED touchscreen is large and looks good.”
“Atmel’s maXTouch solutions provide unlimited capacitive touch capabilities, great linearity and advanced touch screen functionality,” said Chris Ard, Senior Director of Touch Marketing, Atmel.
“These solutions also support the touch of a finger, stylus and even touches from a user with gloves on. The rapid response time and rejection of unintended touches enable Samsung to create the most powerful and intuitive user interfaces for their new product developments, such as the Wave.”
Actel to display SmartFusion mixed signal FPGAs at ESC 2010
MOUNTAIN VIEW, USA; Embedded Systems Conference 2010: Actel Corp. will be displaying SmartFusion intelligent mixed signal FPGAs in action, offering a compelling solution for high complexity motor and motion control applications.
With SmartFusion’s integrated 32-bit ARM Cortex-M3 microcontroller, programmable analog, on-chip embedded nonvolatile memory (eNVM) and proven low power flash based FPGA fabric, SmartFusion directly address the challenges of motor control design.
The development of smaller and more powerful motors, along with recent advances in high-energy batteries, has opened new markets to a wide range of motorized products. New designs for AC and DC motor control must be highly efficient and consume little power in order to provide longer operation without affecting performance.
The need to adopt smaller, more cost-effective motors in traditional motor applications is also influencing electronic motor control techniques for the industrial sectors. Tremendous technology improvements in semiconductor processes and integration are helping designers face these challenges.
Industry experts are partnering with Actel to leverage the capabilities and strengths of SmartFusion devices for motor control applications to provide solutions to this growing market.
Power and Control Design Inc. is an industry leader in sophisticated motor control design and works with major customers targeting motor control applications.
It is jointly developing SmartFusion intelligent mixed signal FPGA based motor control solutions with Actel and was an early adopter as part of the Actel partner program, developing a suite of reference designs that illustrate the compelling fit realized using SmartFusion devices in high-end motor control applications.
The SmartFusion motor control demo developed by Power and Control Design provides sophisticated simultaneous control of up to four Permanent Magnet Synchronous Motors (PMSM). All motors are controlled in trapezoidal and sinusoidal commutation using Hall effect position sensor input, optical encoder position sensor input or a sensorless mode using Back-EMF input to determine motor position and speed.
TRINAMIC Motion Control GmbH & Co. KG, a leader in embedded motion control, is building on its experience as an Actel partner program FPGA user and participation in Actel’s SmartFusion Lead Customer Program to offer motor control to their customers.
TRINAMIC has developed a variety of motor control solutions to solve high-complexity, space-limited motor control challenges. By taking advantage of SmartFusion’s unique feature set, TRINAMIC created a BLDC motor control block unit for high speed commutation. This unit is a functional block coded in VHDL, with control via register access from the SmartFusion 32-bit ARM Cortex-M3 processor.
With the commutation block implemented in hardware, the Cortex-M3 processor is free to implement higher level control algorithms. Utilizing the SmartFusion intelligent mixed signal FPGA together with a TRINAMIC TMC603A integrated BLDC motor gate driver, customers can implement a complete BLDC motor control with only two components.
With SmartFusion’s integrated 32-bit ARM Cortex-M3 microcontroller, programmable analog, on-chip embedded nonvolatile memory (eNVM) and proven low power flash based FPGA fabric, SmartFusion directly address the challenges of motor control design.
The development of smaller and more powerful motors, along with recent advances in high-energy batteries, has opened new markets to a wide range of motorized products. New designs for AC and DC motor control must be highly efficient and consume little power in order to provide longer operation without affecting performance.
The need to adopt smaller, more cost-effective motors in traditional motor applications is also influencing electronic motor control techniques for the industrial sectors. Tremendous technology improvements in semiconductor processes and integration are helping designers face these challenges.
Industry experts are partnering with Actel to leverage the capabilities and strengths of SmartFusion devices for motor control applications to provide solutions to this growing market.
Power and Control Design Inc. is an industry leader in sophisticated motor control design and works with major customers targeting motor control applications.
It is jointly developing SmartFusion intelligent mixed signal FPGA based motor control solutions with Actel and was an early adopter as part of the Actel partner program, developing a suite of reference designs that illustrate the compelling fit realized using SmartFusion devices in high-end motor control applications.
The SmartFusion motor control demo developed by Power and Control Design provides sophisticated simultaneous control of up to four Permanent Magnet Synchronous Motors (PMSM). All motors are controlled in trapezoidal and sinusoidal commutation using Hall effect position sensor input, optical encoder position sensor input or a sensorless mode using Back-EMF input to determine motor position and speed.
TRINAMIC Motion Control GmbH & Co. KG, a leader in embedded motion control, is building on its experience as an Actel partner program FPGA user and participation in Actel’s SmartFusion Lead Customer Program to offer motor control to their customers.
TRINAMIC has developed a variety of motor control solutions to solve high-complexity, space-limited motor control challenges. By taking advantage of SmartFusion’s unique feature set, TRINAMIC created a BLDC motor control block unit for high speed commutation. This unit is a functional block coded in VHDL, with control via register access from the SmartFusion 32-bit ARM Cortex-M3 processor.
With the commutation block implemented in hardware, the Cortex-M3 processor is free to implement higher level control algorithms. Utilizing the SmartFusion intelligent mixed signal FPGA together with a TRINAMIC TMC603A integrated BLDC motor gate driver, customers can implement a complete BLDC motor control with only two components.
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