Altera announces immediate availability of next-gen non-volatile MAX 10 FPGAs and evaluation kits

SAN JOSE, USA: Altera Corp. announced the availability of non-volatile MAX 10 FPGAs, Altera’s latest addition to its Generation 10 portfolio.

Using TSMC’s 55 nm embedded flash process technology, MAX 10 FPGAs revolutionize non-volatile FPGAs by delivering dual-configuration flash, analog and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device.

MAX 10 FPGAs are shipping today and are supported by a broad collection of design solutions that accelerate system development, including Quartus II software, evaluation kits, design examples, design services through the Altera Design Services Network (DSN), documentation and training.

MAX 10 FPGAs provide greater system value to users by reducing overall bill-of-material costs while increasing board reliability. The highly integrated, non-volatile FPGAs provide up to 50 percent board area savings compared to other low-cost FPGAs by integrating into a single chip the following key features:

* Up to 50K logic elements
* Flash memory blocks (user flash and dual-configuration flash)
* Analog-to-digital converters
* Embedded memory and DSP blocks
* DDR3 external memory interfaces
* Embedded processing with soft-core Nios® II processors
* Up to 500 user I/O
* Integrated power regulator.

These key features provide higher system-level value to customers by enabling MAX 10 FPGAs to perform several important system functions, such as an instant-on configuration, fail-safe upgrades, system monitoring and system control.

Synopsys announces new additions to Liberty to significantly speed up timing closure

MOUNTAIN VIEW, USA: Synopsys Inc. announced the completion of an initiative to unify and standardize on-chip variation (OCV) extensions to the open-source Liberty library format, the de-facto modeling standard for integrated circuit (IC) implementation and signoff.

Recent extensions that complete the unified OCV feature set were ratified on August 1, 2014 by the Liberty Technical Advisory Board (LTAB), an IEEE-ISTO federation member program representing the broad semiconductor design ecosystem.

The new variation technology is immediately supported by Synopsys' design platform ecosystem comprised of SiliconSmart® library characterization, IC Compiler place and route, Library Compiler library checker and compiler, and PrimeTime ADV signoff timing and noise analysis solutions.

LTAB members collaborated to consolidate various modeling formats such as advanced on-chip variation (AOCV), parametric on-chip variation (POCV) and statistical on-chip variation (SOCV) into a single, unified open-source standard for industry-wide use, known as the Liberty Variation Format (LVF) extensions.

Unanimously approved by the LTAB board, the latest LVF additions include extensions for slew-load dependent transition and constraint sigma variation tables. These extensions provide designers with a modeling technique that may further reduce timing margins for advanced process nodes, including FinFET, thereby boosting timing closure turnaround-time.

This achievement represents the culmination of a phased approach in collaboration with industry leaders to ensure broad ecosystem enablement from foundry data and model availability, library characterization and modeling know-how, EDA tool chain support, and ROI impact assessment. The board also welcomed some new members, including Samsung.

TSMC and Synopsys accelerate custom design productivity for 16FF+ process

MOUNTAIN VIEW, USA: Synopsys Inc. announced that it has collaborated with TSMC to develop an expanded 16FF+ custom design reference flow using Synopsys' custom design solution.

Part of TSMC's design infrastructure, the expanded custom reference flow adds new technologies to the schematic and layout environment to streamline and accelerate custom design for TSMC's 16FF+ process.

Highlights of these improvements include new methods for design constraints management, estimation of layout-dependent effects prior to final layout, schematic-driven layout with FinFET devices, a simplified method to run pre- and post-layout simulation, and a streamlined graphical user interface for layout of matched devices and guard rings.

"Our customers need EDA tools, a design methodology and IP to all be in place when they are ready to adopt a new process technology," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "We worked closely with Synopsys to ensure that complete custom design solutions for the 16FF+ process node are available to our customers."

In 16FF+ design, circuit designers need a smooth path for communicating constraints to the layout designer, and Synopsys provides a comprehensive solution for constraint management. Design constraints such as device matching, color assignment, symmetry and clustering can be added to schematics and passed to the layout editor to be enforced during layout.

Additionally, the schematic environment has been updated with a simplified method for running pre- and post-layout circuit simulation and comparing the results. Speeding the analysis of layout parasitics reduces the time it takes to finalize the layout. The schematic environment has also been enhanced to support a schematic-driven layout flow for FinFET devices.

In analog circuits, good device matching is needed to deliver performance margin and production yield. The matching device creator in Laker makes it easier to achieve quality custom layout with updated support for matched placement of FinFET devices.

Now, density-aware device array placement, guard ring creation and dummy insertion are all handled through a simple graphical user interface (GUI). For analyzing layout-dependent effects, the custom design reference flow with Laker and TSMC's LDE-API provides a smooth path for back-annotating extracted device parameters to simulation after placement is completed.

"We have had a multi-year collaboration effort with TSMC in custom design which spans 3D extraction, SPICE modeling, physical verification and improved custom layout productivity. This latest collaboration with TSMC delivers best practices and technologies for custom implementation with FinFET technology," said Bijan Kiani, VP of product marketing at Synopsys. "Customers who have adopted this solution are seeing significant productivity gains while benefiting from the advantages of 16FF+ process technology."

NVIDIA installs first Meridian WS-DP for full wafer electrical fault analysis under production conditions

FREMONT, USA: DCG Systems Inc. announced the first installation of the Meridian WS-DP (WaferScan Direct Probe) at NVIDIA, a leading manufacturer of graphics processors for advanced visual computing.

The Meridian WS-DP was selected for its ability to provide full wafer diagnostic and testing under production conditions, dramatically accelerating development and ramp of 16/14nm and 10 nm technologies.

With time-to-yield being a key to profitability, advanced foundries, integrated device manufacturers and fabless companies can no longer afford the limitations of conventional electrical fault analysis tools, which are only able to isolate critical electrical defects at the dicing and packaging stages.

The Meridian WS-DP removes this limitation by providing optical electrical fault isolation (EFA) on full wafers using production testers, load boards, and probe cards, greatly accelerating time to defect localization. In addition, no modifications to wafer sort test programs are required, ensuring precise defect localization accuracy as well as faster workflow set-up between fabless manufacturers and their foundries.

Intel rose to no. 2 position in tablet applications processors in Q2 2014

BOSTON, USA: The global tablet applications processor (AP) market registered a solid 23 percent year-on-year growth to reach $945 million in Q2 2014, according to Strategy Analytics Handset Component Technologies (HCT) service report, "Tablet Apps Processor Market Share Q2 2014: Intel Grabs Number Two Spot."

According to this Strategy Analytics report, Apple, Intel, Qualcomm, MediaTek and Samsung captured the top-five tablet AP revenue share spots in Q2 2014. Apple maintained its tablet AP revenue share lead with 26 percent revenue share, followed by Intel with 19 percent revenue share and Qualcomm with 17 percent revenue share.

According to Sravan Kundojjala, senior analyst: "The non-Apple tablet AP market leadership position continues to change hands and during Q2 2014 it was Intel's turn. Strategy Analytics notes that previously six companies held the non-iPad tablet AP leadership position, which continues to be a challenging one to sustain. Strategy Analytics believes that Intel is on a good trajectory to achieve its 40 million tablet AP shipment goal in 2014."

Stuart Robinson, director of the Strategy Analytics Handset Component Technologies service, adds: "During Q2 2014, HiSilicon, Marvell, MediaTek, NVIDIA and Qualcomm all registered significant shipment growth in the tablet AP market. Strategy Analytics believes that NVIDIA is well-positioned to grab high-profile tablet design-wins with its 64-bit Tegra K1 chip in the second half of 2014."

Microsemi intros SmartFusion2 advanced development kit

ALISO VIEJO, USA: Microsemi Corp. announced the availability of the company's new largest density, lowest power SmartFusion2 150K LE System-on-Chip (SoC) FPGA Advanced Development Kit.

Board-level designers and system architects can quickly develop system-level designs by using the two FPGA Mezzanine Card (FMC) expansion headers to connect a wide range of new functions with off-the-shelf daughter cards, which significantly reduces design time and cost when creating new applications for communications, industrial, defense and aerospace markets.

"Microsemi's new SmartFusion2 150K LE Advanced Development Kit is ideal for designers developing low power, high security and highly reliable SoC applications," said Shakeel Peera, senior director of product line marketing at Microsemi.

"With our largest density 150K LE device onboard, the development kit will enable customers to design applications for the complete SmartFusion2 family. Additionally, designers can accelerate their time-to-market and reduce development costs for high density designs by leveraging the two industry-standard FMC headers to develop or access pre-designed functional blocks on off-the-shelf daughter cards."

The new SmartFusion2 SoC FPGA Advanced Development Kit offers a full featured 150K LE device SmartFusion2 SoC FPGA. This industry-leading low power 150K LE device inherently integrates reliable flash-based FPGA fabric, a 166 MHz Cortex M3 processor, digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded nonvolatile memory (eNVM) and industry-required high-performance communication interfaces—all on a single chip.

Microsemi estimates its market for FPGAs to be around $2.5 billion. This is based on estimates garnered from iSuppli and competitive financial reports which report on revenue for individual product families.

The new FMC headers provide designers additional cost savings, the ability to accelerate design development, and helps significantly reduce time-to-market on designs by providing the opportunity to leverage a wide range of standard off-the-shelf daughter cards for applications such as image and video processing, serial connectivity (SATA/SAS, SFP, SDI) and analog (A/D, D/A).

The release of this kit also complements Microsemi's expertise and IP in JESD204B, supporting the growing enterprise market for high speed data conversion for applications such as radar, satellite, broadband communications and communications test equipment.

Micrel selects Dongbu HiTek to manufacture camera flash LED drivers for smartphones and tablets

SEOUL, SOUTH KOREA: Dongbu HiTek confirmed that it has been selected by Micrel Inc. to manufacture the Silicon Valley company’s recently introduced camera flash LED drivers for smart phones, tablet computers and digital cameras.

Now in volume production, Micrel’s ultra-compact LED drivers are being manufactured with Dongbu HiTek’s specialized 0.18um Analog CMOS process.

Operating at high switching frequencies (2.0MHz/4.0MHz), the new LED drivers specify miniature inductors and capacitors that reduce the total silicon power footprint to less than 10mm squared. The new drivers can be controlled via robust single-wire serial interface, which allows the host processor to control LED current and brightness.

Dongbu HiTek’s AN180 process at the 0.18um node is ideally suited to implement these highly integrated drivers as it adds the benefit of efficient power management with an on-chip boost converter.

“Micrel continues to distinguish itself as an industry leader in high performance linear and power solutions,” said Jae Song, Dongbu HiTek EVP of Marketing. “We look forward to further collaborating with Micrel to apply our specialized analog and mixed-signal processes in developing power management ICs for mobile applications.”

According to iSuppli, the global market for power management ICs targeting mobile handsets and media tablets is expected to grow from approximately $2.3 billion in 2013 to more than $3.3 billion in 2017, promising a CAGR of nearly 9 percent over this period.

Dongbu HiTek’s AN180 Analog CMOS process offers a handy repertoire of analog functions as well as dense 1.8V logic and 5V CMOS that can operate efficiently at moderate power levels. The mixed-signal functions embodied in the Korean foundry’s specialized BCDMOS (BD180LV) process may be modularly incorporated into the AN180 process. Coupled with popular EDA software and certified libraries, the versatile AN180 process minimizes design risk and speeds time to volume production.

Cadence and ARM expand SoC design collaboration with multi-year technology access agreement

SAN JOSE, USA & CAMBRIDGE, ENGLAND: Cadence Design Systems Inc. and ARM announced the signing of a multi-year Technology Access Agreement.

Expanding upon the successful EDA Technology Access Agreement signed in May 2014, this new agreement gives Cadence rights to access to existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink System IP, ARM Artisan physical IP, and ARM POP IP.

This partnership enables ARM and Cadence to continue providing customers with advanced low-power and high-performance system-on-chip (SoC) design solutions for markets including next-generation mobile, consumer, networking, storage, automotive and IoT.

"Together, ARM and Cadence have delivered robust solutions that have enabled developers, designers and engineers to create innovative new ARM-based devices," said Pete Hutton, executive VP and president of product groups, ARM. "This new agreement is a strong commitment from both companies to continue delivering the key technologies and tools the design community needs when creating world-class products and pushing the boundaries of innovation."

Additional features of the agreement include the ability for Cadence to develop optimized processor scripts and flows for Mali GPUs and the latest high performance ARM processors, including the recently announced ARM Cortex-M7 core for embedded applications.

The collaboration between Cadence and ARM on the Cortex-M processor family leverages Cadence's proven integrated mixed-signal design and verification flow and expertise in low-power design and verification for applications including IoT end-node device implementation. Early access to Artisan Physical IP enables Cadence to optimize its physical design tools to achieve aggressive power, performance and area targets.

The agreement also complements the previously existing collaborations between ARM and Cadence around implementation and verification of ARM's 64-bit ARMv8 architecture Cortex-A50 processor series, the integration of ARM Fast Models with Cadence Palladium XP series hardware for fast hybrid virtual emulation, and performance verification and analysis for CoreLink 400 interconnect IP-based systems using Cadence's Interconnect Workbench solution.

ARM and Synopsys expand collaboration

CAMBRIDGE, UK & MOUNTAIN VIEW, USA: ARM and Synopsys Inc. have signed a multi-year subscription agreement that expands Synopsys' access to a broad range of ARM intellectual property (IP) and related technologies to enable optimization of Synopsys tools and methodologies for ARM-based system-on-chips (SoCs).

Through this agreement, Synopsys has pre-production access to ARM Cortex processors for the ARMv8-A and ARMv7-A architectures, ARM Mali graphics processors, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP for implementation acceleration.

Building on more than 20 years of collaboration as well as the August 2012 license agreement between the companies for ARMv7-A processors and related IP, this new agreement allows Synopsys to further optimize its design flows and tools for ARM-based SoCs, enabling designers to meet their power, performance and area goals, while reducing cost and time-to-market.

"We have collaborated extensively with Synopsys for more than 20 years to ensure our mutual customers can get innovative products to market quickly and still meet their performance, power and area targets," said Pete Hutton, executive VP and president of product groups, ARM. "With Synopsys' early access to our latest IP and our ongoing close collaboration, we can provide our customers solutions that work effectively together as they design, implement and verify their SoCs."

With this agreement, Synopsys can develop and distribute optimized Synopsys tool scripts to ARM partners and deliver training on the use of Synopsys tools and flows with the ARM IP. Synopsys' early access to ARM pre-production IP ensures that early licensees of the latest ARM cores have optimized tools and methodology in place when they are ready to begin their design projects.

Designers creating products for a broad range of markets, including wearable, mobile, networking and server, will benefit from closer integration of the Synopsys tools and ARM IP together with optimized design flows that can take advantage of process technologies ranging from leading-edge FinFET to mature processes.

Building on the foundation of the companies' previous collaborations, which have delivered solutions that span implementation, verification, system architecture design and software development, this new agreement allows the companies to extend these results to benefit designers using the latest ARM IP. Reference Implementations (RIs) for ARM processors, library and POP IP with Synopsys Galaxy implementation tools deliver optimized power, performance and area.

These RIs together with tool optimizations have led to numerous tape out successes for mutual customers with ARM's most advanced IP, including the Cortex-A57 CPU, Cortex-A53 CPU and Mali-T760 GPU. Designers using Synopsys' VCS functional verification and ZeBu emulation solutions benefit from significantly enhanced simulation performance for ARM processors and perform hardware/software debug on Synopsys' Verdi debug platform with direct support for ARM Cortex processors.

Verification engineers are verifying the cache-coherent subsystems in their SoCs, taking advantage of Synopsys verification IP (VIP), ZeBu transactors and Verdi Protocol Analyzer support of the ARM AMBA® interface specification, including the latest, AMBA 5 CHI. Software developers are using Virtualizer Development Kits (VDKs) for ARM processors to perform early software development, architects are using Synopsys' Platform Architect MCO for early power and performance optimization of ARM-based systems and system designers are using HAPS FPGA-based prototyping to accelerate hardware/software integration and validation of systems based on ARM CPUs and GPUs.

Designers benefit not only from these design solutions, but also Synopsys' field expertise and Core Optimization Services developed over many years of enabling ARM-based design success. ARM, Synopsys and mutual customers will present examples of these successes at the upcoming ARM TechCon, Oct. 1-3, 2014, in Silicon Valley.

"Designers benefit directly from this alignment of the industry's IP and EDA leaders," said Deirdre Hanford, executive VP, customer engagement at Synopsys. "Through collaboration with ARM, we've been able to accelerate many leading semiconductor companies' innovations. This new agreement will allow us to deliver timely design and verification solutions that take advantage of Synopsys' latest tools and methodology together with ARM's newest, most advanced IP."

Coverity launches Code Spotter in free beta version

MOUNTAIN VIEW, USA: Coverity, Inc., a Synopsys company, announced the launch of Coverity Code Spotter, a cloud-based service enabling developers to find hard-to-detect defects in Java code. Built on Coverity's static code analysis technology, Code Spotter is available for free to the software development community during the beta period.

Using Code Spotter, developers can upload as much Java source code as they would like to the service. The service is designed to find the most common and critical issues in Java code bases, including resource leaks, race conditions, concurrency issues, control flow issues, null pointer dereferences, issues detected by the open source FindBugs tool, copy and paste errors, and many other software defects resulting in incorrect or unpredictable program behavior.

"There are more than six million professional software developers in the world writing at least 60 million lines of code every day, which means the need for a simple-to-use, lightweight process for testing software quality and security has never been more critical," said Dennis Chu, senior product manager for Coverity. "With Code Spotter, we've aimed to do just that by expanding our SaaS offerings to provide even more developers across the globe with tools that make it easier to produce high-quality software."

Code Spotter works by integrating with developers' build systems. It intercepts and compiles the source code files that are part of a project, and then uploads them to the Code Spotter servers for analysis. Once the analysis job is complete, developers can examine the results on the Code Spotter website or download the results for review locally.

TVS to champion requirements driven verification and test at DVCon Europe

BRISTOL, UK: TVS, a leader in software test and hardware verification solutions, announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel.

The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.

DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits.  DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.

AT DVCon Europe, TVS will be presenting two papers and one tutorial:

• TVS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.

• TVS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by TVS’s Suresh Babu in partnership with Roman Wang of AMD.

• TVS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by TVS’s Mike Bartley and Serrie Chapman.

Leading-edge IC foundry market to increase 72 percent in 2014

USA: IC Insights has just released its September Update to The McClean Report, a 30-page report that contains Part 2 of a detailed analysis of the IC foundry market and its players as well as an updated 2014 forecast for the semiconductor industry capital spending outlays by the leading 36 semiconductor companies worldwide.

Moreover, the September Update includes the first forecast and discussion regarding 2015 capital expenditures by the top 10 spenders, which currently represent 80 percent of industry-wide semiconductor capital spending.

Of the big four pure-play foundries (i.e., TSMC, GlobalFoundries, UMC, and SMIC), TSMC is the only one that is expected to have a higher revenue-per-wafer figure in 2014 than in 2010.

Of the big four foundries, TSMC is forecast to have the highest revenue per wafer in 2014 at $1,328, 27 percent higher than GlobalFoundries. In contrast, UMC’s revenue per wafer in 2014 is expected to be only $770, 42 percent less than TSMC’s revenue per wafer. Although the average revenue per wafer of the big four foundries is forecast to be $1,145 in 2014, the actual revenue per wafer is highly dependent upon feature size.

Fig. 1 shows the typical 2Q14 revenue per wafer for select major technology nodes and wafer sizes produced by the Big 4 foundries.  As shown, there is more than a 14x difference between the 0.5µ 200mm revenue per wafer ($430) and the 28nm 300mm revenue per wafer ($5,850).  Even when normalizing the figures by using the revenue per square inch, the difference is dramatic ($51.77 for the 28nm technology versus $8.56 for the 0.5µ technology).

Although TSMC has a very large percentage of its sales targeting ≤45nm production, its 2014 revenue per wafer is still forecast to be up only 14 percent when compared to 2009.

IC Insights believes that the entrance of GlobalFoundries and Samsung into the high-end foundry market over the past few years has put pressure on TSMC to keep its prices for leading-edge products competitive.  Although there will probably be only five foundries able to offer high-volume leading-edge foundry production over the next five years (i.e., TSMC, GlobalFoundries, UMC, Samsung, and Intel), these companies are likely to be fierce competitors and pricing will likely be under pressure as a result.

Before GlobalFoundries entered the foundry market, TSMC was by far the technology leader among the major pure-play foundries. In 2014, 60 percent of TSMC’s revenue is expected to be from ≤45nm processing.  As expected, with GlobalFoundries’ fabs having a large portion of their capacity dedicated to producing AMD’s MPUs over the past few years, its processing technology is skewed toward leading-edge feature sizes.  In 2014, 57 percent of GlobalFoundries’ sales are forecast to be from ≤45nm production.

Although GlobalFoundries is expected to have a similar share of its sales dedicated to ≤45nm technology as TSMC in 2014, TSMC is forecast to have almost 6x the dollar volume sales at ≤45nm as compared to GlobalFoundries this year ($14.8 billion for TSMC and $2.5 billion for GlobalFoundries).

In contrast, only 15 percent of SMIC’s 2014 sales are expected to come from devices having ≤45nm feature sizes, which is the primary reason why its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

As shown in Fig. 2, the vast majority of the increase in pure-play foundry sales in 2014 is forecast to be due to ≤28nm feature size device sales.  Although it is expected to represent 71 percent of total pure-play foundry sales in 2014, the >28nm pure-play IC foundry market is forecast to increase only 4 percent this year.

In contrast, the 2014 leading-edge ≤28nm pure-play foundry market is expected to be about $5.1 billion, a 72 percent increase in size as compared to 2013. Not only is the vast majority of pure-play foundry growth coming from leading-edge production, most of the profits that will be realized come from the finer feature sizes as well.

ST intros world’s first ARM Cortex-M7 Core-based STM32F7 series MCU

GENEVA, SWITZERLAND: STMicroelectronics announced the extension of its STM32 family of more than 500 pin- and software-compatible microcontrollers.

The new STM32 F7microcontroller (MCU) series leverages the ARM Cortex-M7 core, just announced as ARM’s newest and most powerful Cortex-M processor. ST’s STM32 F7series leapfrogs the industry’s previous high-performance 32-bit Cortex-M champ — ST’s own STM32F4—in delivering up to twice as much processing and DSP performance that is accessible via a seamless upgrade path.

Headlining the industry’s most successful family of Cortex M-core-based microcontrollers, the new STM32F7 MCU series operates at frequencies up to 200MHz and uses a 6-stage superscalar pipeline and Floating Point Unit (FPU) to produce up to 1000 CoreMarks.

Architectural innovations surrounding the MCU boost performance and ease of use: ST has included two independent mechanisms to reach 0-wait-state performance from both internal and external memories: using ST’s Adaptive Real-Time (ART Accelerator) for internal embedded Flash and L1 cache for both execution and data access from internal and external memories.

Mentor Graphics and TSMC to deliver IC design and signoff infrastructure for 10nm

WILSONVILLE, USA: Mentor Graphics Corp. has entered into a 10nm collaboration with TSMC.

Physical design, analysis, verification and optimization tools have been enhanced to meet 10nm FinFET process requirements for early customers' test chip and IP design starts. The infrastructure includes the Olympus-SoC™ digital design system, the Analog FastSPICE (AFS™) Platform including AFS Mega, and the Calibre signoff solution.

"TSMC and Mentor are doing extensive engineering work that enables mutual customers to take full advantage of advanced process technologies," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Each node requires a tremendous amount of innovations to address new physical challenges, and to increase accuracy for customers' design enablement, while also providing increased performance and reduced turnaround time."

Calibre provides the layout pattern's full-coloring capability to help designers specify color assignments independent of the design cockpit for 10nm rules compliance. For custom layouts, the Calibre RealTime product has been enhanced to enable interactive color checking while designing with all leading custom layout tools, using foundry-certified Calibre signoff decks.

Mentor and TSMC have also enhanced the Calibre fill solution for 10nm FinFET designs. The SmartFill ECO functionality in Calibre YieldEnhancer supports a "fill-as-you-go" flow ensuring that IP and other design blocks are accurately represented as the design progresses.

When part of the design is modified, the SmartFill ECO feature can re-fill just the affected portions to minimize turnaround time. Likewise, Calibre LVS has been enhanced to maintain design hierarchy for efficient post-layout simulation at advanced process nodes such as TSMC's 10nm.

The two companies have also partnered to make the Mentor Olympus-SoC place and route system ready for TSMC's 10nm FinFET requirements. Significant enhancements have been made to the database, placement, clock tree synthesis, extraction, optimization and routing engines to make them 10nm FinFET compliant.

To ensure accurate circuit simulation of 10nm FinFET devices, Mentor collaborated with TSMC to validate BSIM-CMG and TMI models for high-speed device and circuit level simulation on the Analog FastSPICE Platform, including AFS Mega. New 10nm FinFET models are also supported by Calibre xACT™ extraction product and the Calibre nmLVS™ product.

Cadence unveils broad IP portfolio for TSMC 16nm FinFET Plus process

SAN JOSE, USA: Cadence Design Systems Inc. announced a broad portfolio of intellectual property (IP) for TSMC's 16nm FinFET Plus (16FF+) process.

The wide array of IP for the 16FF+ process enables systems and semiconductor companies to take advantage of the 15 percent speed improvement with same total power or 30 percent total power reduction at the same speed compared to the16FF process.

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs. Silicon-tested IP is expected to be available beginning in Q4 2014. For detailed protocol information and availability details, customers should contact their local Cadence salesperson.

Cadence also announced today the qualification of its digital implementation, signoff and custom/analog design tools for the 16nm FinFET Plus process. Click here for more information.

"Our new 16nm FinFET Plus process is an important development for next-generation SoC designs as they balance the task of increasing performance while reducing power and area," said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. "As a long time trusted TSMC partner, we believe Cadence will play a vital role in the broad adoption of this new process with its certified tools and IP portfolio."

Intel and Tsinghua Unigroup to accelerate development and adoption of Intel-based mobile devices

SANTA CLARA, USA: Intel Corp. and Tsinghua Unigroup Ltd, a solely state-owned limited liability corporation funded by Tsinghua University inChina, jointly announced that both parties have signed a series of agreements.

The purpose of the agreements is to expand the product offerings and adoption for Intel-based mobile devices inChina and worldwide by jointly developing Intel Architecture and communications-based solutions for mobile phones. Intel also has agreed to invest up to RMB 9 billion (about $1.5 billion) for a minority stake of approximately 20 percent of the holding company under Tsinghua Unigroup which will own Spreadtrum Communications and RDA Microelectronics, subject to regulatory approvals and other closing conditions.

Both Spreadtrum and RDA, controlled by Tsinghua Unigroup, are leading fabless semiconductor companies inChina, which develop mobile chipset platforms for smart phones, feature phones and other consumer electronics products, supporting 2G, 3G and 4G wireless communications standards.

"China is now the largest consumption market for smartphones and has the largest number of Internet users in the world," said Brian Krzanich, Intel CEO. "These agreements with Tsinghua Unigroup underscore Intel's 29-year-long history of investing in and working inChina. This partnership will also enhance our ability to support a wider range of mobile customers inChina and the rest of the world by more quickly delivering a broader portfolio of Intel architecture and communications technology solutions."

Cadence digital and custom/analog tools achieve TSMC certification for 16FF+ process, collaborate on 10nm FinFET

SAN JOSE, USA: Cadence Design Systems Inc. announced that its digital and custom/analog tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process.

This will enable systems and semiconductor companies to take advantage of the 15 percent speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to be concluded by November 2014.

Cadence also collaborated with TSMC to make several enhancements to its Custom Design Reference Flow (CDRF) for the 16FF+ process. Additionally, Cadence and TSMC are collaborating on the 10nm FinFET process, and Cadence solutions are ready to support 10nm early customer design starts.

The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. Cadence tools certified for 16FF+ include Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ QRC Extraction Solution, Virtuoso® custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor.

Enhancements to the CDRF include an exclusive TSMC application programming interface (API) incorporated into Virtuoso Analog Design Environment GXL that speeds up statistical simulation flow, a new design methodology leveraging module generator (ModGen) technology for designing FinFET arrays to avoid density gradient effects, and the introduction of the electrically aware design (EAD) platform to extract and analyze real-time parasitics and electromigration (EM) violations during design implementation.

Cadence tools in the flow include Virtuoso custom design platform, Integrated Physical Verification System, Physical Verification System, Quantus QRC Extraction Solution, Spectre simulation platform, Voltus-Fi Custom Power Integrity Solution and Litho Electrical Analyzer.

Cadence also announced today a broad portfolio of intellectual property (IP) for TSMC's 16nm FinFET Plus (16FF+) process.

Smartphone connectivity presents opportunities and challenges for automotive processor chip suppliers

EL SEGUNDO, USA: The use of smartphones in motor vehicles—already a near-ubiquitous phenomenon—is the most disruptive trend in the automotive infotainment business today, presenting both challenges and opportunities for automakers and their processor semiconductor suppliers, according to a new report from IHS Technology.

The most promising prospect for automotive processors in the years ahead will be in the telematics portal head unit, which can connect with a smartphone for mobile broadband connectivity.

Revenue for automotive infotainment processor chips for telematics portal head units will grow to $508 million in 2018, up from slightly less than $128 million in 2013. While this particular application accounted for only 8 percent of total global automotive infotainment processor market revenue in 2013, its share will surge to 30 percent in 2018.

In comparison, the automotive processor segment with the highest revenue last year, head units for navigation, will shrink dramatically by 2018. Revenue will plunge to $51.0 million in 2018, down from $367.8 million in 2013, as navigation becomes a standard feature provided not only by multimedia and telematics portals but also by smartphones.

“Smartphone use in vehicles has led to two divergent approaches to head-unit designs, one replacing smartphone and the other one embracing them,” said Tom Hackenberg, senior analyst for microcontrollers and microprocessors at IHS. “For the most part, automakers are heeding the call to accommodate mobile devices. This explains the dramatic rise in revenue for telematics portal head units, which address the complexities of the human-machine interface as well as the increasing consumer demand for ubiquitous connectivity.”

To keep up with such consumer preferences, automotive original equipment manufacturers (OEM) are providing systems that are more extensively integrated. Not only will infotainment systems come with features such as networked displays, controls built into the steering wheel and large touch screens, cars will also be able to capitalize on users’ smartphones to connect with the various integrated systems of the vehicle, in order to offer a richer and more up-to-date experience.

The great growth in new features from automotive OEMs is expected to take market share away from aftermarket vendors, which will be hard-pressed to exceed the rich user experience delivered from pre-installed and highly integrated infotainment systems.

Hitting the right mix
Some crucial challenges will face vehicle OEMs when developing media-rich cars. A feature-laden infotainment solution adapted from a consumer electronics design has a potential risk, however insignificant, of introducing previously unknown flaws or clashing with critical systems electronically. This can create a liability issue in vehicle design.

Also, excess or inappropriate infotainment can be construed as driver distraction—another liability for the OEM.

On the other hand, such concerns must be weighed against the potential for an inadequate user experience if car makers offer unsophisticated smartphone connectivity options, which could tarnish brands and make them seem irrelevant.

Striking the correct balance—between a safe driving experience on the one hand, and the evolving demands of the connected consumer on the other—is creating a narrow but contentious design challenge for next-generation vehicle infotainment, Hackenberg noted.

The demand for a user experience commensurate with smartphones and tablets has additional implications for automotive infotainment, Hackenberg added. The disparity between the rapid development cycle of multimedia processors and the carefully tested development cycle of automotive OEMs means that the infotainment system designer must be creative in enabling flexible product-line solutions to accommodate a rapidly changing supply chain.

Another hurdle for automotive OEMs is to match consumer expectations of their infotainment experience. In this case, vehicle owners may want their connectivity interaction with the car’s infotainment system to look and feel the same as when they deal with their portable devices.

The problem is especially acute because mobile handsets come and go at a rapid pace, with new models and updates developing and introduced during a period of one year or less. Automotive makers, meanwhile, need to maintain a consistently high standard of quality, and it could take years to implement the new developments in connectivity, such as those related to interfacing with mobile devices like smartphones.

For the premium vehicle market, which is more likely to embrace multimedia and Internet connectivity features by replacing the need for a smartphone, this connotes designing a more modular and costly approach that can evolve at the pace of mobile technologies. For the more mainstream market embracing the smartphone for processing applications, this will mean a constant struggle with mobile device compatibility.

Micrel launches 85V full bridge MOSFET driver addressing technology advances in battery operated tools

SAN JOSE, USA: Micrel Inc. has introduced the MIC4606, a 85V Full Bridge MOSFET driver that features Adaptive-Dead-Time and Shoot-Through Protection.

The device is part of Micrel's highly successful 85V MOSFET Driver family first launched in 2013 and is designed to focus on the growing power needs of multiple applications. The 85V MIC4606 family is part of Micrel's strategy to address battery powered tools, uninterrupted power supplies, radio controlled toys and the growing drone market.

The MIC4606 is currently available in volume with pricing starting at $1.37 for 1K quantities in a 4mm x 4mm QFN package.

"The ubiquitous powered tool market has been quietly undergoing technological advances by adding control algorithms to enhance user productivity, safety and product longevity. Micrel's 85V Full Bridge MOSFET driver offers advanced circuitry such as Adaptive-Dead-Time for high power efficiency and Shoot-Through Protection for enhanced reliability," noted Brian Hedayati, VP of marketing, high-performance Linear and Power Solutions, Micrel.

"The MIC4606 is one of the industries' most robust and power efficient Full Bridge MOSFET drivers designed to address a wide variety of applications including stepper motors, DC brushed and brush less motors, and DC/AC inverters."

The MIC4606 combines a full array of features and technology solutions all designed to maximize power efficiency. The Adaptive-Dead-Time circuitry actively monitors the Full Bridge to minimize time between high and low side MOSFET transitions. The Anti-Shoot-Through circuitry prevents erroneous inputs and noise from turning on both MOSFETs at the same time. The device also offers a wide 5.5V to 16V operating supply range that also maximizes system efficiency.

The low 5.5V operating voltage allows for longer run time in battery powered applications. These features combine to make the MIC4606 an ideal solution for the industry's most demanding battery operated motor applications including power tools and power DC/AC inverters. In addition, the 85V operating voltage offers plenty of margins in order to protect against voltage spikes that are typical in motor drive and power supply circuitry.

The MIC4606 is available in a tiny 16 pin 4mm × 4mm QFN package with an operating junction temperature range of -40-degC to +125-degC.

Altera and China Mobile Research Institute announce joint efforts on next gen C-RAN wireless technologies

HONG KONG: Altera Corp. announced a  three-year strategic agreement with China Mobile Research Institute (CMRI) to research and prototype next generation of green wireless network  infrastructure solution  based on the Centralized Radio Access Network (C-RAN) architecture that leverages network function virtualization (NFV).

The agreement was signed on August 15 in Beijing, China, at the 2014 International Mobile Internet Conference, which is organized and sponsored by the Chinese Ministry of Industry and Information Technology and the three major Chinese operators including China Mobile.

Also at the event, Francis Chow, VP and GM of Altera’s Communications Business Unit,  presented  on how Altera FPGA technology is enabling green C-RAN architecture with an emphasis on performance, connectivity, and scalability.

200mm wafer equiv will grow to over 200 million units

USA: In 2014, semiconductor units are expected to grow over 5 percent to reach a new record, and wafer demand growth is a direct result of these numbers.

Every quarter, Semico releases our Quarterly Wafer Demand Forecast & Summary to analyze changes in the market so you can strategize for the next quarter.

"As expected during the first half of 2014, semiconductor sales were robust," says Joanne Itow, Semico's MD. "Unit sales in wireless communication continue to be strong as smartphone manufactures prepare to rollout new phone models in the fall."

The Semico unit forecast is one of the main inputs to the wafer demand model.  Other inputs include process technology by product, die sizes, yields and wafer size.

On a regular basis, Semico analyzes semiconductor products by manufacturing technology, die size, yields, and technology roadmaps.  This information is based on data collection over the past 20 years and interviews with hundreds of companies.  Semico performs this data collection for a wide variety of semiconductor device types.

Some of the key findings include:
* Wafer demand is expected to grow by 7.4 percent in 2014.
* Mobile DRAM will see high growth.
* Total wafer demand will grow to over 200 million 200mm wafer equivalents.
* Total memory wafer demand will increase by 4.2 percent in 2014.

ST unveils thin-film piezoelectric MEMS technology

GENEVA, SWITZERLAND: STMicroelectronics announced that it is commercializing its innovative piezoelectric MEMS technology.

This innovation combines the company's long-established leadership in high-volume MEMS design and manufacturing with the many new application opportunities offered by piezoelectric technology.

ST's TFP (Thin-Film Piezoelectric) MEMS technology is a foundational process platform that can be readily customized, allowing ST to work with customers around the world to jointly develop specific MEMS products, optimized for particular applications.

One of the first customers to take advantage of ST's TFP process is poLight, whose innovative TLens® (Tuneable Lens) uses a piezoelectric actuator to change the shape of a transparent polymer film, imitating the focussing function of the human eye.  This makes it the ideal solution for camera auto-focus (AF) applications, which up till now have mostly relied on large, power-hungry, and expensive Voice Coil Motors (VCM).

ARM supercharges MCU market with high performance Cortex-M7 processor

CAMBRIDGE, UK: ARM has unveiled a new 32-bit Cortex-M processor that delivers double the compute and digital signal processing (DSP) capability of today’s most powerful ARM-based MCUs.

The ARM Cortex-M7 is targeted at high-end embedded applications used in next generation vehicles, connected devices, and smart homes and factories. Early licensees of the Cortex-M7 processor include Atmel, Freescale and ST Microelectronics.

“The addition of the Cortex-M7 processor to the Cortex-M series allows ARM and its partners to offer the most scalable and software-compatible solutions possible for the connected world,” said Noel Hurley, GM, CPU group, ARM. “The versatility and new memory features of the Cortex-M7 enable more powerful, smarter and reliable microcontrollers that can be used across a multitude of embedded applications.”

The Cortex-M7 achieves an impressive 5 CoreMark/MHz[i]. This performance allows the Cortex-M7 to deliver a combination of high performance and digital signal control functionality that will enable MCU silicon manufacturers to target highly demanding embedded applications while keeping development costs low.

Expected uses of Cortex-M7 include smart control systems employed in a range of applications such as motor control, industrial automation, advanced audio, image processing, a variety of connected vehicle applications and other Internet of Things (IoT) uses.

Enabling faster processing of audio and image data and voice recognition, the benefits delivered by the Cortex-M7 processor will be immediately apparent to users. The core also provides the same C-friendly programmer's model and is binary compatible with existing Cortex-M processors.
Ecosystem and software compatibility enables simple migration from any existing Cortex-M core to the new Cortex-M7. System designers can therefore take advantage of extensive code reuse which in turn offers lower development and maintenance costs.

In 2013, ARM’s partners shipped some 3 billion ARM-based MCUs, making it the industry-leader in its class.

Artesyn add-on acceleration card enables high density video processing in standard servers and cloud networks

HONG KONG: Artesyn Embedded Technologies has announced the SharpStreamer add-on acceleration card that enables content owners, broadcasters and service provider networks to speed the deployment of high density video transcoding and multiscreen delivery.

Using the standard PCI Express form factor, Artesyn's SharpStreamer offers quick and scalable integration with standard server architectures to meet the demands of service providers and operators who want to use existing servers and cloud infrastructure to support new video transcoding and adaptive bitrate delivery platforms.

Compared with dedicated appliances, SharpStreamer acceleration is more easily deployable and does not constrain broadcasters and operators to dedicated equipment in order to monetize OTT streaming content. It also enables networks to scale as subscriber numbers increase, by adding more cards and density from small to large servers as needed.

Compared to software-only solutions, the SharpStreamer add-on card requires a fraction of the server and operational cost to enable video processing services.

This latest addition to Artesyn's add-on video acceleration card portfolio is focused on the high-density and low power demands of video streaming applications such as over-the-top (OTT) streaming servers, mobile network optimization, content delivery networks (CDN), and broadcast secondary distribution.

iPhone 6 Plus: $100 costlier for consumers to buy—just $15.50 more expensive for Apple to make

EL SEGUNDO, USA: For consumers opting to buy Apple Inc.’s iPhone 6 Plus rather than the iPhone 6, the additional 0.8 inches of screen size will cost $100 extra. However, for Apple, the iPhone 6 Plus costs only about $16 more to produce, delivering to the company an even heftier margin than normal for its wildly popular smartphone line.

The bill of materials (BOM) of the iPhone 6 equipped with 16 gigabytes (GByte) of NAND flash memory amounts to $196.10, according to a preliminary estimate by the Teardown Mobile Handsets Intelligence Service at IHS Technology. The cost of production rises to $200.10 when the $4.00 manufacturing expense is added.

The BOM of the iPhone 6 Plus amounts to $211.10, and rises to $215.60 with the additional $4.50 manufacturing cost added. This is only $15.50 higher than the total for the iPhone 6.

“Apple has always been adept at offering higher-end iPhone models with enhanced, desirable features—and then pricing those versions for maximum profitability,” said Andrew Rassweiler, senior director, cost benchmarking services for IHS.

“In the past, the premium versions of iPhone offered higher memory configurations for additional profit.  While Apple continues this memory strategy, the company is also taking a similar approach with the iPhone Plus, structuring its pricing to add bottom-line profit on models that have a very desirable feature: a large phablet-sized display.”

With a contract from a wireless operator, the 16GByte version of the iPhone 6 is priced at $200, while the Plus model amounts to $300. The unsubsidized pricing for the two phones is $649 and $749, respectively.

Phablet fees
The most obvious difference between the two new Apple smartphone models is the display, with the iPhone 6 sporting a 4.7-inch screen, and the Plus coming in at 5.5 inches. However, while the larger screen is more expensive, it doesn’t account for the entire cost differential between the two phones; the Plus also carries higher BOMs for its enhanced camera and battery subsystems.

For both the iPhone 6 and iPhone 6 Plus models, the screens feature in-touch in-plane switching (IPS) liquid crystal displays (LCD) supplied by two sources: LG Display and Japan Display. The displays likely employ Corning’s Gorilla 3 glass, compared to Gorilla 2 in the iPhone 5S and 5C.

Due to its larger size, the display/touch-screen subsystem in the iPhone 6 Plus carries a cost of $52.50, compared to $45.00 for the iPhone 6.

Both displays are also more expensive than for the smaller, 4-inch display/touch subsystem used in the iPhone 5S model, at $41.00, based on pricing from October 2013.

Battery boost
The larger form factor of the iPhone 6 Plus allows it to employ a bigger, higher-capacity battery. The iPhone 6 Plus battery has a capacity of 11.1 watt-hours (Wh), compared to 6.91 Wh for the iPhone 6. Because of this, the battery subsystem in the Plus is $1.00 more expensive than in the iPhone 6.

Also, owing to their larger sizes, the iPhone 6 and iPhone 6 Plus both have more capacity than the 5S, which came in at just 5.92 Wh. Furthermore, the camera of the Plus is $1.50 more expensive than in the iPhone 6.

Samsung and TSMC
In a major departure in component supplier selection from previous models, the critical applications processor chip used in both the new iPhones is not supplied entirely by Samsung.

The new models use the Apple-designed A8 processor, replacing the A7 employed in the iPhone 5S. The A8 exhibits new markings that are not consistent with previous A-series processors. IHS believes that Apple now is splitting its orders for the A8 processor between semiconductor foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Samsung.

The A8 integrates twice the number of transistors as in the previous-generation A7 processor used in the iPhone 5S, but the part is still smaller than the A7 due to the use of more advanced semiconductor manufacturing technology. With its more advanced design and manufacturing, the A8 in the iPhone 6 and iPhone 6 Plus models costs $20.00, compared to $17.00 for the A7 in the iPhone 5S.

Sensor shift
The new-model iPhones also feature some key changes to the sensor/microphone subsystem.

In the individual iPhone 6 and iPhone 6 Plus models analyzed, IHS identified a 6-axis sensor supplied by InvenSense. Previous iPhones torn down by IHS used accelerometers from Bosch Sensortec and Gyroscopes supplied by ST Microelectronics. The new iPhone 6 and 6 Plus feature an accelerometer from Bosch Sensortec and the 6-axis sensor from InvenSense. It may be possible that these parts are multisourced, even though the small number of samples analyzed by IHS does not reveal this.

The new iPhones also add a barometric sensor, marking the first time Apple has employed this type of sensor in its smartphone line.

Despite some reports to the contrary, the iPhone 6 and iPhone 6 Plus contain the same AKM electronic compass used in previous models.

NFC champion
To support the new Apple Pay feature, the new iPhones add a near-field communication (NFC) chip, another first for Apple’s smartphones. The latest phones include the PN65V NFC controller from NXP Semiconductors, as well as a previously unseen NFC-booster integrated circuit from AMS.

TeraSquare to unveil ground breaking reverse gearbox IC for next gen 100Gbps networks

SOUTH KOREA: TeraSquare Inc. will reveal the worlds’ first MLG2.0 single chip solution for 100G networks, at this year’s ECOC exhibition.

The new IC is the first for the market and will revolutionize the industry by enabling 10GE and 40GE channels to be used at 100G data rates, whilst dramatically improving signal quality and making massive power consumption savings.

The MLG2.0 is a reverse gearbox for CDR applications that converts up to ten 10GE channels or a combination of 10GE and 40GE channels up to 100G.

It is designed for next-generation 100G small form factor modules such as CFP2, CPF4 and QSFP28 and is fully compliant to OIF. The IC only consumes 1.4W of power and has all of the features of the TeraSquare 100G parallel CDR launched last year.

Upgrading to 100Gbps data-rate is progressing rapidly within the market, as well as a big increase in the number of ports using legacy data-rate 10GE and 40GE. These rates are set to be widely used for the next 10 years, leaving the market with a huge demand in solutions that can support the legacy data-rate at 100Gbps data rate with increasing port density.

MLG2.0 is the right solution for this demand that is set to hit the market. TeraSquare is already working on the future beyond MLG2.0, MLG3.0 is currently being standardized and will include a forward-error-correction (FEC) function.

ST unveils industry’s most flexible and highest-performance integrated wideband RF synthesizer

GENEVA, SWITZERLAND: As the number of wireless standards and frequency bands grow to support an ever-expanding number of applications, STMicroelectronics is supporting both the demand for higher performance and integration.

The introduction of the STW81200 RF synthesizer leverages ST’s BiCMOS (SiGe) manufacturing technology by integrating in one chip wideband voltage-controlled oscillators (VCOs), a dual fractional and integer phase-locked-loop (PLL) core, low-noise voltage regulators, plus a set of programmable hardware options to comply with a wide variety of RF requirements.

In applications such as base stations, radio links, satellite, communications, and test and measurement, overall system performance is tightly linked to RF synthesizer phase noise characteristics. These applications demand integration and cost optimization with no compromise in RF performance.

In meeting these requirements, the STW81200 as the industry’s most flexible RF synthesizer supports development of multi-band, multi-standard software-defined radios across the wide frequency range of 50MHz to 6GHz,while delivering normalized in-band phase-noise floor of -227 dBc/Hz, a VCO phase noise of -135 dBc/Hz @1MHz offset with a 4.0GHz carrier, and a noise floor of -160 dBc/Hz.

The STW81200 is unique in its ability to be powered from a single unregulated supply at 5V, 3.6V, or 3.0V and tuned in consumption and performance extending the application range from traditional mains-powered infrastructure to battery-powered devices.

AMD FirePro W8100 delivers 38X more performance than closest competing product

GOA, INDIA: AMD India launched the AMD FirePro W8100 professional graphics card, enabling new levels of workstation performance delivered by the company’s second generation, industry-leading AMD Graphics Core Next (GCN) architecture.

With nearly 38 times the performance of the closest competing product based on double precision testing designed for the next generation of 4K CAD (Computing-Aided Design) and Media and Entertainment (M&E) workflows, engineering analysis and supercomputing applications.

Bolstering the AMD Professional Graphics product family with yet another productive workstation solution, the AMD FirePro W8100 features a best-in-class 8 GB of GDDR5 memory, up to 4.2 TFLOPS of single precision compute performance, and unmatched double precision compute performance of up to 2.1 TFLOPS.

“With an increase in availability and accessibility of 4K displays, there has been a rise in the applications demanding increased memory support while pushing the limits of real-time 4K video production and rendering. The addition of AMD FirePro W8100 is a significant step towards expanding our product portfolio for enabling professionals – in cooperation with our hardware and software partners – with the best kind of workstation performance that they need for supercomputing applications and next generation 4K workflows,” said Raja Koduri, corporate VP, Visual Computing, AMD.

AMD flagship professional graphics deliver ultimate real-time 4K experience for next gen workstations

GOA, INDIA: AMD India launched the AMD FirePro W9100 professional graphics card designed for the next generation of 4K workstations accelerated by OpenCL (Open Computing Language).

With cutting-edge graphics, up to 2.62 TFLOPS double precision of industry leading GPU compute power ultra-high resolution (4K) multi-display capabilities, video, design and engineering professionals can work at a whole new level of detail, speed, responsiveness and creativity.

With an industry first 16GB of ultra-fast GDDR5 memory, workstation users can multi-task efficiently across layer in multiple effects to 4K video projects, all in real-time. Powered by AMD’s latest Graphics Core Next architecture, AMD FirePro W9100 gives creative professionals supercomputing-class performance from a single GPU.

“The AMD FirePro W9100 is designed to deliver ultimate visual supercomputing performance for the next generation, ultra high-resolution workflows. This professional graphics card is optimized and certified for leading workstation applications and ensures ultra-high geometry performance and smooth handling of complex models,” said Raja Koduri, corporate VP, AMD Visual Computing.

Synopsys tools achieve TSMC certification for 16-nm FinFET+ process and entered 10-nm FinFET collaboration

MOUNTAIN VIEW, USA: Synopsys Inc. announced that TSMC has certified a comprehensive list of Synopsys' custom and digital design tools for their 16-nm FinFET+ processes.

The V0.9 certifications are all completed and V1.0 certification is on-track and to be concluded by November, 2014. The two companies have also entered N10 collaboration. With needed tool enhancements in place to meet 10-nm FinFET process requirements, customers can now use Synopsys tools for their 10-nm design starts.

Collaboration between TSMC and Synopsys is enabling customers to deploy Synopsys' industry-leading digital and custom tools to take advantage of the power, performance and area benefits of the 10-nm and 16-nm process technologies.

The extensive engineering collaboration between Synopsys and TSMC facilitated delivery of key technologies including routing rules, physical verification runsets, extraction technology files, interoperable process design kits (iPDKs) and a reference flow for the N16FF+ process. System-on-Chip (SoC) design teams can now deploy the silicon-proven, project-ready Synopsys solution to implement FinFET-based designs.

"Our deep and extensive collaboration with Synopsys on critical design-enablement technologies has continued beyond the N16FF process," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division at TSMC. "Jointly, Synopsys and TSMC are addressing our customers' needs to deliver highly optimized design solutions for N10FF and N16FF+ process geometries."

"Our goal is to enable our mutual customers to maximize the power, performance and area benefits of the 10nm and 16-nm FinFET process technologies," said Bijan Kiani, VP of product marketing, Design Group, at Synopsys. "This extensive technology collaboration spans the digital and custom tools to allow engineers to deliver their next-generation designs in a productive and predictable manner."

AMD launches AMD Radeon R9 285 graphics

GOA, INDIA: AMD India has launched the AMD RadeonTM R9 285 graphics card, serving as the newest desktop GPU in the award-winning AMD Radeon R9 series graphics family.

The Radeon R9 285 graphics card brings the robust feature set of AMD’s Radeon R9 290 series graphics, like support for Project FreeSync and AMD TrueAudio technology, to even more gamers. The AMD Radeon R9 285 graphics card has been designed to run the most demanding games with ultimate settings at 1080p and beyond.

AMD first unveiled the AMD Radeon R9 285 graphics card during its 30 Years of Graphics & Gaming event on August 23, 2014. It comes packed with the latest Graphics Core Next (GCN) Architecture upcoming DirectX 122 and AMD’s revolutionary Mantle API engine clock speed of 918 MHz, and 2 GB of frame buffer running at 5.5 Gbps.

The Radeon R9 285 GPU is capable of delivering up to 3.29 teraFLOPS of computing performance, offering extreme gaming detail that outshines any card at 1080p and beyond in its category. Custom and overclocked AiB SKUs are available today.

eInfochips ranked among top global engineering services companies for 2014

AHMEDABAD, INDIA: eInfochips, the leading engineering and design services company, has strong solution presence on the Global Service Providers Ratings (GSPR) 2014 released by Zinnov Management Consulting.

The Annual GSPR 2014 Report reinforces eInfochips leadership capabilities on key parameters such as Innovation, IP Focus, Specialization, R&D Practice Maturity, Breadth and Depth of Services, and Ecosystem Linkages, among others.

eInfochips has made significant advances on software solutions for Internet-of-Things (IoT), Business Intelligence (BI), Big Data Analytics and Cloud Computing. With the capability to deliver end-to-end solutions, the company features in the execution zone for consumer and e-commerce software. This adds a new dimension to eInfochips traditional strength in semiconductor and embedded systems.

Microchip expands low-cost 8-bit PIC MCU portfolio

USA: Microchip Technology Inc. has announced a new addition to its PIC12/16LF155X 8-bit microcontroller (MCU) family with the PIC16LF1554 and PIC16LF1559 (PIC16LF1554/9) devices.

The PIC16LF1554/9 includes two independent 10-bit 100K samples per second Analog-to-Digital Converters (ADC) with hardware Capacitive Voltage Divider (CVD) support for capacitive-touch sensing. This unique ADC configuration enables more efficient sensor acquisition and assists with advanced touch-sensing techniques for extremely noisy environments, low-power applications, matrix keypads and water-resistant designs.

The 14- and 20-pin PIC16LF1554/9 MCUs combine up to 17 ADC channels with automated hardware CVD modules to implement capacitive sensing and other front-end sampling applications with minimal software overhead.

These devices also include up to 14 KB Flash/512 Bytes RAM, a 32 MHz internal oscillator, two PWM modules, along with I2C, SPI and EUSART for communications. Additionally, they are eXtreme Low Power (XLP) compliant with active and sleep currents of 35 µA/MHz and 30 nA, respectively, for applications where energy conservation is paramount.

ST unveils thin-film piezoelectric MEMS technology

GENEVA, SWITZERLAND: STMicroelectronics announced that it is commercializing its innovative piezoelectric MEMS technology. This innovation combines the company's long-established leadership in high-volume MEMS design and manufacturing with the many new application opportunities offered by piezoelectric technology.

ST's TFP (Thin-Film Piezoelectric) MEMS technology is a foundational process platform that can be readily customized, allowing ST to work with customers around the world to jointly develop specific MEMS products, optimized for particular applications.

One of the first customers to take advantage of ST's TFP process is poLight, whose innovative TLens (Tuneable Lens) uses a piezoelectric actuator to change the shape of a transparent polymer film, imitating the focussing function of the human eye.  This makes it the ideal solution for camera auto-focus (AF) applications, which up till now have mostly relied on large, power-hungry, and expensive Voice Coil Motors (VCM).

"Piezoelectric actuators and sensors can now be manufactured in our Agrate 8" Fab that has produced billions of motion sensors, taking full advantage of ST's long-standing position as the world's leading manufacturer of MEMS devices," said Anton Hofmeister, Group VP and GM of Custom MEMS Division, STMicroelectronics. "Our TFP MEMS technology rewrites the script, opening up new cost/benefit scenarios that will, in turn, enable many new applications."

The pilot line for ST's new TFP MEMS platform was partially funded by the European LAB4MEMS program. The technology has many important potential applications for actuators like inkjet printheads in Commercial, Industrial and 3D printing, but can also be used to develop piezo sensors in fields like energy harvesting.  ST is targeting volume production for its pilot customers in mid-2015.

Pulsed RF power semiconductor device markets will exceed $300 million by 2019

SCOTTSDALE, USA: Markets for pulsed RF power devices up to 18 GHz are expected to show continued growth over the next five years despite the current economic turmoil and cuts in defense spending. While their association with consumer spending fuels the volatility of many global electronics markets, pulsed RF power devices are supported by quite different priorities.

“Many RF power semiconductor manufacturers are on a quest to find markets unrelated to mobile wireless infrastructure,” notes ABI Research director, Lance Wilson. “Device prices in wireless infrastructure are falling, and the total available market is flattening out.”

Some markets that use pulsed RF power devices, such as transportation safety and military, are experiencing solid growth even in the midst of today’s economic downturn. These devices are used in radars for military, weather and marine applications, and in the current worldwide upgrade of the air traffic control system. There is also a market segment devoted to the avionics transponder and air navigation market, which is also lifted by the overall air traffic control upgrade.

Intrinsically less “optional” than many consumer markets, these segments are therefore less sensitive to economic upheavals than consumer-driven markets, although they are not totally immune to the macro economy.

Understanding this, many semiconductor manufacturers are attempting to enter this market space; however, some factors may complicate their efforts. Pulsed RF power device markets are becoming very competitive technologically: gallium nitride and silicon carbide devices are vying for market share along with the more established silicon and gallium arsenide based technologies.

However, the market may not be able to support all the new entrants. “Undoubtedly some consolidation will continue to occur. While not guaranteed success, those companies that have a track record working with government agencies and defense contractors are going to have an advantage over those that are new entrants,” adds Wilson.

Among the leaders for high-power RF pulsed semiconductor devices are M/A-COM Technology Solutions, TriQuint, Microsemi, NXP Semiconductors, Cree, Sumitomo Electric Device Innovations, and Integra Technologies.

Open-Silicon expands front-end design capabilities with advanced virtual prototyping solution

MILPITAS, USA: Open-Silicon is expanding its virtual prototyping capabilities with support for a new web portal introduced by Carbon Design Systems.

Called Carbon System Exchange, the portal provides access to more than 100 pre-built virtual prototype systems and subsystems. These pre-built systems, known as Carbon Performance Analysis Kits (CPAKs), speed the creation and optimization of application-specific integrated circuit (ASIC) and System-on-Chip (SoC) designs. CPAKs include software, intellectual property (IP) and system solutions from numerous vendors. Open-Silicon has contributed multiple CPAKs to the portal.

"Open-Silicon adds value throughout the entire system design process, from initial concept and architecture through to manufacturing and packaging, making it critical that we have access to the most advanced and accurate virtual prototyping solutions," said Huzefa Cutlerywala, senior director of technical solutions for Open-Silicon.

"We are already using CPAKs internally to deliver optimized ARM processor-based designs, and have found that CPAKs enable us to increase our productivity and accuracy -- ultimately lowering cost and reducing schedule risk for customers. By making CPAKs available directly to our customers via Carbon System Exchange, we expect to build on these existing design advantages."

As part of its support, Open-Silicon has contributed three CPAKs to the portal. The first is a system model containing an ARM® Cortex-A7 dual core platform with memory models. The memory models, developed by Open-Silicon, include NOR flash and SD/eMMC.

The CPAK facilitates the development of low level firmware, such as boot ROM and bootloaders, and also enables driver development. Integrated memory models, built from memory specifications, allow end users to read and write their code into memory without the need for an FPGA or ASIC. Open-Silicon has also contributed an ARM Cortex M3 processor CPAK, as well as a performance analysis CPAK for DSP-based designs. Open-Silicon intends to add more CPAKs as they are developed.

NXP becomes world's first supplier to deliver V2X chipset for mass-production secure connected cars

EINDHOVEN, THE NETHERLANDS: NXP Semiconductors announced a significant breakthrough for automotive drivers around the world.

For the first time, V2X chipsets will be put into high-volume manufacturing. NXP will supply Delphi Automotive PLC with its RoadLINK chipset for Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) communication.
The wireless technology significantly improves road safety by alerting drivers of critical traffic information. Having secured a partnership with a leading global automaker, Delphi's platform will be first to market and is expected to be on the roads in as little as two years.

Using NXP's technology combined with application software from Cohda Wireless, Delphi's platform allows alerts to be delivered to vehicles from other cars and surrounding infrastructure, such as traffic lights and signage to alert drivers about potentially hazardous traffic situations even beyond the line of sight, optimally complementing Advanced Driver Assistance Systems (ADAS) like radar.

Messages could include blind-intersection collision, road condition hazards, road works, presence of emergency vehicles, stationary or slow moving vehicles, traffic jam, and accident warnings, as well as traffic signals or signage indicators.

The solution avoids cellular or other networks that can be slow or unreliable, instead operating on IEEE 802.11p, a wireless communication standard designed for the needs of the automotive industry, and directly connects surrounding infrastructure and vehicles to each other to achieve immediate transmission and ensure reliable road safety communications. The V2X communication is protected against illegal attacks or data theft by NXP's V2X hardware security module.

MaxLinear launches MxL231 and MxL235 programmable gain amplifiers

CARLSBAD, USA: MaxLinear Inc. announced the MxL231 and MxL235 upstream programmable gain amplifiers (PGAs) for use in DOCSIS 3.0 and upcoming DOCSIS 3.1 gateways, respectively.

PGAs are utilized to amplify upstream communications from DOCSIS gateways back to head-end equipment.

Complementing the company’s popular Full-Spectrum Capture (FSC) receivers for 16-, 24-, and 32-channel DOCSIS 3.0 gateways, the MxL231 reduces front-end power dissipation by up to 1.6W compared to existing PGA offerings. As cable operators migrate from four-channel to eight-channel QAM upstream services, reducing power dissipation in the front-end simplifies thermal design efforts and reduces heat mitigation costs.

Additionally, the MxL231 has a smaller footprint than existing PGA devices and requires fewer external components, thereby reducing the PCB area required for upstream amplification. Using only a single 3.3V supply, the MxL231 now allows manufactures to eliminate the 5V supply from their gateway design entirely, simplifying layout and reducing system cost.

Leveraging design architecture similar to the MxL231, the MxL235 is optimized to meet the higher upstream power output required in the DOCSIS 3.1 standard. The MxL235 can deliver any combination of DOCSIS 3.0 and DOCSIS 3.1 channels up to a combined output power of 69dBmV. The MxL235 will be offered as a companion to MaxLinear’s upcoming DOCSIS 3.1 FSC receivers.

Microsemi intros first product in Timberwolf family.ZL38040

ALISO VIEJO, USA: Microsemi Corp. has introduced the first product in its new Timberwolf family. Powered by Microsemi's AcuEdge acoustic technology, the ZL38040 delivers best-in-class high definition (HD) voice communication solutions for the enterprise hands-free speakerphone markets.

Microsemi's ZL38040 is a new device with an advanced wideband acoustic echo canceller designed to provide leading-edge echo cancellation and noise reduction for HD audio speaker phone and IP phone applications. Microsemi's patented AcuEdge firmware and its acoustic echo canceller permit significantly more audio information to be transmitted while blocking interfering signals such as echo and background noise.

AcuEdge's technology consists of license-free, royalty-free audio IP solutions. It is the compilation of various intellectual properties targeted at processing voice signals in conjunction with noise reduction algorithms, automatic gain control, echo cancellation, psychoacoustic noise reduction, howling detection and rejection.

These powerful capabilities are the foundation for enterprise level automatic speech recognition, sound classification and other intelligent decision-making functions based on sound and audio detection.

Synopsys unveils Verification Continuum

MOUNTAIN VIEW, USA: Synopsys Inc. announced the Synopsys Verification Continuum platform to accelerate industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs.

Verification Continuum is built from Synopsys' market-leading and fastest verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning and coverage technology. Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs.

"AMD's advanced multi-core Accelerated Processor Unit designs require a continuum of verification technologies working seamlessly together to meet growing hardware and software verification requirements," said Alex Starr, fellow and pre-silicon solutions architect at AMD.

"Synopsys Verification Continuum represents an important new direction for the industry, and our initial evaluation of the technology indicates it can accelerate design schedules with a more efficient and scalable platform optimized for complex SoC verification and early software bring-up."

The mobile and Internet of Things (IoT) markets are driving dramatic increases in SoC complexity and software content along with intensifying time-to-market pressure. To address these challenges, SoC teams require many verification technologies such as simulation, emulation and prototyping across the spectrum of pre-silicon verification, post-silicon validation and early software bring-up.

Today, engineers spend months of effort in design bring-up and transition effort between disjoint technologies, further complicated by the need to debug across domains and to support large software teams. To shorten SoC time-to-market, leading teams are adopting "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up.

Synopsys' Verification Continuum enables these shift-left strategies with best-in-class verification technologies unified with seamless design bring-up, transition and debug throughout the flow.

Industry's fastest verification engines
Synopsys' Verification Continuum is built from the industry's fastest verification engines including Virtualizer virtual prototyping, Verification Compiler static and formal technologies, VCS simulation, ZeBu emulation, HAPS FPGA-based prototyping and Verdi3 debug.

These best-in-class technologies provide the performance and capacity that industry leaders depend on to verify many of the world's largest and most complex chips.

Unified compile with industry-leading VCS
Verification Continuum features Unified Compile based on the mature VCS simulator front-end, providing a robust simulation-like user experience across the verification flow, that enables engineers to easily transition between simulation, static and formal verification, emulation, FPGA-based prototyping and debug as required by the verification task.

Existing flows based on individual point tools require extensive setup for each tool in the flow, and weeks or months of effort to move a design between different tools based on varying language support or other requirements. Unified Compile with VCS eliminates this redundant work, saving months of effort in typical project schedules.

Unified debug with Verdi
Unified Debug based on Synopsys' Verdi3 environment provides a consistent debug user experience across the verification flow, optimized with Verification Continuum technologies for even higher productivity. Verdi3 has long been recognized as the leading open debug platform, and as part of the Verification Continuum, it provides a single interface for multi-domain debug across virtual prototyping, static and formal verification, simulation, emulation and FPGA-based prototyping.

Since bugs may exist on the boundary between traditional verification domains, Verdi3 also enables fully synchronized, mixed-abstraction debug between SPICE, RTL, transactions and software.

Scalable FPGA-based emulation and prototyping
As SoC complexity and software content increase, leading SoC development teams have concluded that commercial FPGA-based hardware-assisted verification is the best, most scalable approach to meet the growing demand for high-performance platforms for early software bring-up and SoC verification.

Verification Continuum integrates FPGA-based emulation and prototyping seamlessly into mainstream verification flows, helping to save weeks to months in design bring-up time compared with earlier approaches. Verification Continuum's Unified Compile technology has been architected to support FPGA-based verification platforms, delivering up to 3X faster compile time for Synopsys' ZeBu Server-3 emulation system.

"The Verification Continuum requires an optimized software flow combined with the highest-performance, highest-capacity emulation and prototyping hardware," said Victor Peng, executive VP and GM of the Programmable Products Group at Xilinx. "Xilinx has raised the bar again with our Virtex® UltraScale devices, offering the largest 20nm FPGA in the industry, the XCVU440. We are working closely with Synopsys to optimize our Vivado® Design Suite flow to address the unique requirements of hardware-assisted verification users."

"Synopsys' Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry," said Manoj Gandhi, senior VP and GM of the Verification Group at Synopsys. "The significant verification R&D investments Synopsys has made over the past two years are already showing promising early results towards helping customers reduce time-to-market by months for advanced SoC designs."

Early availability is scheduled for December 2014, with general availability in 2015.

TVS joins MIPI Alliance, intros MIPI verification IP suite

BRISTOL, UK: TVS, a leader in software test and hardware verification solutions, announced that it has joined the MIPI Alliance, which develops interface specifications for mobile and mobile-influenced industries.  The move reflects the demand for TVS’ Verification IP, especially in the mobile application sector that is moving quickly and thus creating new opportunities for the company.

Mike Bartley, CEO and founder of TVS commented: “Companies developing IP and chips for the mobile SoC market recognise the importance of getting to market quickly with designs that work. These factors are of the utmost importance and so make VIP an obvious choice.”

The Verification IP (VIP) supplied by TVS follows a well-defined development process that starts with a feature extraction based on the interface specification from the MIPI Alliance. Not only does this provide a common start point with the client but importantly, an independent development of the VIP. All the VIP deliverables are also linked to the specification through the feature extraction, thus making it easier for users to understand the objectives of the VIP.

TVS’s MIPI VIP suite, offered as part of its asureVIP portfolio, continues to expand. The company is also working closely with a number of customers to develop new VIP or to update existing VIP to reflect new MIPI Alliance standards or new versions of existing standards. Potential clients can be confident in the quality of TVS VIP through evaluation of existing VIP.

Bartley added: “The fact that TVS delivers VIP with source code also gives the client several advantages including no license issues and easier debug. Our clients find that larger companies are not quite so flexible as TVS and we are also able to respond more quickly to the new MIPI Alliance standards.”

Connect One launches next gen IoT WiFi modules

KFAR SABA, ISRAEL: Connect One, the Device Networking Authority, has launched its next-generation (G2) WiFi modules to support the latest 802.11b/g/n wireless standards for the Internet of Things (IoT) market.

With the rapid advances in IoT infrastructure, many applications such as medical, security, industrial control, smart grid, asset management, and point of sale, need the fastest, more secure wireless standards for their communications. G2 incorporates these latest standards at up to 40 percent savings, while creating a no-change upgrade path for customers.

In addition to preserving form, fit, and function of existing modules, Connect One has enhanced and enriched the functionality available across the entire G2 line:

* Full 802.11b/g/n support (previously available only on Connect One MAX modules).
* Easy switching between WiFi Access Point and WiFi Client Operation modes.
* Industrial temperature range of -30°C to +85°C.

The G2 modules offer excellent system performance for IoT connectivity with Broadcom BCM43362 WiFi Transceiver SOC and its 802.11b/g/n MAC and baseband functionality. The G2 modules build on this foundation and Connect One’s iChip Internet Controller, providing multiple hardware interfaces, extensive firmware, and a full suite of secure Internet protocols for WiFi client mode and up to eight WiFi users in router or access-point modes.

Designers gain immediate, full-featured connectivity without any WiFi driver development or porting, minimizing project development challenges and time to market.

Lattice announces production of MachXO3L devices in WLCSP and caBGA packages

HILLSBORO, USA: Lattice Semiconductor Corp. announced volume production of its industry-leading MachXO3LTM family in four tiny packages as small as 2.5 mm x 2.5 mm.

Lattice also launched two new low-cost breakout boards that enable designers to evaluate the MachXO3L device’s hard IP, versatile I/O and other capabilities. These releases solidify the MachXO3L family’s lead in enabling engineers to quickly solve complex design problems in applications as diverse as industrial infrastructure and smart connected devices.

“Lattice is clearly ahead of its competition with a rich 25-year legacy of instant-on products,” said Keith Bladen, corporate VP, Marketing. “Our non-volatile FPGA portfolio leads the industry with advanced 40 nm technology, power as low as 19 μW and the industry’s widest density range with 256 to 40K LUT devices in production today. The demand for MachXO3L devices is strong and growing with nearly 200 unique customers across a wide range of markets including industrial, communications and consumer.”

More industrial segments adopt SiC technology

LYON, FRANCE: Silicon Carbide (SiC) propagates over all industrial segments, announced Yole Développement (Yole), the market research, technology and strategy consulting company.

Power factor corrector (PFC), photovoltaic inverter, motor control, and more represented a $100 million business in 2013.

Yole released last week, its SiC technology and market analysis: SiC Modules, Devices and Substrates for Power Electronics Market report. The company updated its investigation and give us its vision of the SiC industry.

This 2014 edition includes a bill-of-material comparison SiC versus Si at the system level, a payback-time simulation and detailed market data. This report is a complete analysis of the SiC industry at the device, module and substrate levels, in the power electronics field; it shows the involvement of key SiC players, the state-of-the art technology. This study also reviews all manufacturing costs and key economics of SiC technology.

Atmel expands world-class wireless portfolio with 802.11b/g/n Wi-Fi SoCs and modules

SAN JOSE, USA: Atmel Corp. announced the company has expanded its leading SmartConnect wireless portfolio with two new turn-key system-on-chips (SoCs) and four new modules featuring these SoCs.

Atmel's WILC1000 and WINC1500 SoCs extend its already broad portfolio of wireless connectivity options with the latest 802.11b/g/n Wi-Fi capability, seamlessly integrating Newport Media's (NMI) solutions in just two months. Atmel acquired NMI in July 2014.

Both wireless solutions are compatible to existing Atmel MCU solutions and can connect to any Atmel AVR or Atmel SMART MCUs. The new WINC1500 is an IEEE 802.11b/g/n IoT network controller, while the WILC1000 is an IEEE 802.11b/g/n IoT link controller.

Expanding on Atmel's Wi-Fi offering, the WILC1000 and WINC1500 are SoC solutions optimized for battery-powered IoT applications. These wireless SoCs feature fully integrated power amplifiers for the industry's best communication range, without compromising cost or performance.

The WILC1000 and WINC1500 are add-on solutions, which can connect to any Atmel MCU or eMPU targeting a wide range of Internet of Things (IoT), consumer and industrial applications. Both products are available either as fully-certified modules ready for production to accelerate a designer's time-to-market or as discrete SoCs for customers requiring the highest design flexibility.

Mentor Graphics delivers commercial Mentor Embedded Linux platform and graphics enablement for AMD embedded G-series and R-series devices

WILSONVILLE, USA: Mentor Graphics Corp. announced the availability of the Mentor Embedded Linux software for the AMD Embedded G-Series SoC (previously codenamed: "Steppe Eagle"), CPU (previously codenamed: "Crowned Eagle") and 2nd Generation R-Series APU (previously codenamed: "Bald Eagle") devices.

Developers who began evaluation, prototyping, and development by downloading the previously announced and freely available Mentor Embedded Lite and Sourcery™ CodeBench Lite products can now easily migrate to these new commercially-supported versions.

Developers can make use of the Mentor Embedded Linux (MEL) and the Sourcery CodeBench integrated development environment (IDE) products to create dynamic applications targeting markets such as digital gaming, point-of-sale (POS), and electronic signage/displays.

AMD Embedded customers can take advantage of the commercial version of the MEL product on the AMD Embedded G-Series and R-Series platforms by quickly building, from source, a customized Linux-based platform based on technology from the Yocto Project.

Using the Mentor Embedded Sourcery CodeBench and award-winning Sourcery Analyzer technology, embedded C/C+ developers can gain valuable insights into system behavior and timing through a visual debugging framework that identifies functional, timing, and performance bottlenecks.

For embedded graphics and user interface (UI) development, the commercial MEL platform includes the integrated, accelerated Qt 5 and graphics framework and accelerated GStreamer media stack (OpenMax). This feature is an open source solution based on the Qt Project, used by over 450,000 developers worldwide.

In addition to the Qt library modules, developers can make use of unique system-level trace and analysis visualization to easily optimize UI performance metrics, such as frame rate, to deliver highly responsive graphics-intensive applications.

TI's 100G transimpedance amplifier drives high performance in optical networking systems

DALLAS, USA: Texas Instruments (TI) introduced its first transimpedance amplifier (TIA) for the 100G optical networking market.

As a key component of the system, the ONET2804T brings high levels of sensitivity with negligible cross-talk penalty and low input-referred noise (IRN) to provide stable and robust communication in hot-pluggable transceivers.

The newest member of TI's broad optical networking portfolio, the 100G TIA serves parallel optical interconnects in applications with data rates of up to 28 Gbps, such as optical line cards, point-to-point microwave backhauls and video over fiber.

MediaTek Labs developer program for simplified creation of portable and IoT devices

HSINCHU, TAIWAN: MediaTek launched Labs on the market, a global initiative, which developers of any background knowledge or knowledge of portable devices and IoT (Internet of can develop things).

The new program provides developers, manufacturers and service providers Software Development Kits (SDKs), Hardware Development Kits (HDKs), technical documentation, and technical and managerial support.

"With the launch of MediaTek Labs we open for everyone - from amateurs on students to professional developers and designers - a new world of possibilities in which creativity and innovation are no limits," says Marc Naddell, VP of MediaTek Labs. "We are convinced that the benefits of activities MediaTek Labs innovations will lead the next wave of consumer gadgets and apps that will cure billions of things and people around the world."

The Labs Developer Program includes the LinkIt-Entwickler platform based on the MediaTek Aster (MT2502) chipset based. The LinkIt developer platform is one of the most effectively networked platforms with outstanding integration for the package size and requires no additional hardware for connectivity.

With LinkIt and the proven reference model for developing design of MediaTek prototype portable and IoT devices can be easily and inexpensively created. The LinkIt platform consists of the following components:

Vesper launches with very high SNR MEMS mic tech

BOSTON, USA: Intending to improve the smallest audio component found in smartphones, wearables and Internet of Things (IoT) devices, a new Boston-based sensor company called Vesper has designed a microphone that will enhance consumers' acoustic experience with voice capture and sound recording.

Though such microphones are virtually invisible to consumers, the market for the highest-performance devices is huge: the research firm IHS predicts that it will reach $718 million by 2017i.

Vesper's microphone technology offers the highest signal-to-noise ratio (SNR) in ultra-compact form factors for consumer microphones: 70 db SNR, which is the key determining factor in acoustic performance.

Consumers demand a better acoustic experience with their mobile devices. However, current MEMS microphone technology has been lacking, limiting the quality of always-on voice command, which is prone to high rates of error, and high-fidelity sound recording, particularly in noisy environments.

Users cite 10 percent smaller design sizes with latest releases of Synopsys' Design Compiler

MOUNTAIN VIEW, USA: Synopsys Inc. announced that multiple customers have achieved smaller area using the latest releases of its Design Compiler RTL synthesis solution, a key component of Synopsys' Galaxy Design  Platform.

Aggressive area optimization is critical for designers across a wide range of electronic applications to either lower system costs or implement additional functionality without increasing die size. Innovations in the latest releases include advanced optimizations operating with and without physical information, which lower power and produce smaller, more routable designs without impacting timing.

"Minimizing area and meeting timing requirements enables us to differentiate and deliver value in a highly competitive multi-functional product marketplace," said Michihiro Okada, GM of the Software 3 R&D Division, Corporate Software Development Division at KYOCERA Document Solutions Inc., a leading manufacturer of document imaging solutions and document managing systems.

"Design Compiler's new monotonic area optimization reduced design area by 10 percent for multiple designs while meeting timing requirements and lowering leakage power. This allowed my design team to implement additional functionality without an increase in die cost."

"As a leader in mixed-signal semiconductors for the automotive, industrial and consumer markets, reducing die size is critical to meeting our  business objectives," said Armin Kemna, director Design Support at Elmos Semiconductor.  "We are seeing up to 10 percent reduction in gate count simply by using the latest release of Design Compiler. In addition, technology links between Design Compiler and IC Compiler provided early insight into physical challenges and helped us stay on schedule."

Design Compiler includes new optimization technologies that monotonically reduce design area and leakage power by an average of 10 percent while maintaining timing quality of results (QoR). These area optimizations operate on new or legacy design netlists, with or without physical information and at all process nodes.

Utilizing this new capability, in conjunction with new congestion optimizations, designers can significantly reduce die area and ease design closure without impacting any other QoR metrics. In addition, new RTL analyses and cross probing capabilities accelerate design schedules.

"Smaller die size and shorter design schedules continue to be key requirements for our customers designing at both established and emerging process nodes," said Bijan Kiani, VP of marketing for Synopsys' Design Group. "These new technologies for smaller area and lower power consumption help our customers to be more competitive in their market segments, while strengthening Design Compiler's position as the synthesis tool of choice for designers worldwide."