Thursday, April 4, 2013

Si2’s OpenPDK Coalition releases ESD design flow methodology

USA: The Silicon Integration Initiative (Si2) announced that the ESD (Electro-Static Discharge) Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology “best practices” document for industry-wide adoption in order to promote a more consistent treatment of this important aspect of integrated circuit (IC) design.

At advanced process nodes, it becomes increasingly critical to adhere to strict ESD design guidelines, because inadequate ESD protection can reduce effective yield and thus increase overall costs. This document provides comprehensive guidelines for incorporating ESD protection into IC design flows. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

The design of ESD (Electro-Static Discharge) protection devices in an IC should be evaluated and verified at all stages of a standard circuit design flow starting from the Cell Schematic level and ending at the Full Chip Layout level. A comprehensive set of ESD checks should be verified using appropriate tools at each of these levels to ensure that the integrated circuit has robust ESD protection.

The released document describes the ESD design flow, the various checking tools that are used at each level and the requirements for each of these tools.

The ESD design flow document examines such items as: Schematic Level Checking (Cell & Full Chip Level), Layout Level Checking, Power Bus Resistance Extraction Tool, Floor Planning Level Checking, Evaluation Expectations, and Tool Infrastructure.

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