Tuesday, April 23, 2013

MoSys announces Macnica Americas support of GigaChip interface for high-performance chip-to-chip communications

USA: MoSys announced that Macnica Americas, a leader in semiconductor distribution and design services with expertise in design services, applications support, chip-to-chip communications protocols, and logistics, will support the GigaChip interface in its distribution and technology innovation business.

The GigaChip interface (GCI) is a scalable, high-performance, serial protocol for chip-to-chip communications that is differentiated in efficiency and reliability, resulting in system level benefits of reduced power, cost and complexity. Current implementations built with compatible CEI-11G or XFI SerDes electrical transport standards deliver up to 144 Gigabits per second (Gbps) of full duplex data throughput using 16 SerDes lanes when running at a 10G rate. A key differentiator for the GCI protocol is high transport efficiency, even for small payloads.

 Alternative serial interfaces are typically less than 50 percent efficient when transferring 8 bit and 16 bit data, which means that they deliver less than half the performance at a given bandwidth. The combination of 90 percent transport efficiency, from small to large payloads, with power efficient short reach physical interconnect makes GCI ideal for co-processor, memory, or multi-chip communication.

The interface also includes CRC error detection and automatic error recovery provisions to meet the high reliability requirements of enterprise, service provider, and mission-critical communications and compute applications. GCI is an open, royalty-free interface specification designed for use with MoSys’ Bandwidth Engine family of ICs and is suitable for any chip-to-chip interconnect.

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