Synopsys announces energy-efficient 28-nm PCI Express 3.0 PHY with support for 10GBASE-KR

USA: Synopsys Inc. announced the availability of its multiprotocol DesignWare Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications.

Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express (PCIe) 3.0 and 10GBASE-KR, for a flexible interconnect solution.

The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).

"As the fastest growing protocol in the enterprise and data center market, 10 Gigabit Ethernet is becoming a key backplane interface," said Jag Bolaria, senior analyst at The Linley Group.

"Our research indicates over 25 percent CAGR through 2016 in the number of 10 Gigabit Ethernet ports deployed in the enterprise and data centers. The growth of 10GBASE-KR ports, combined with the rapid adoption of integrated PCI Express 3.0 in multiprocessor cores, elevates the importance of Synopsys' multiprotocol SerDes IP for designers developing ASICs that embed high-speed interfaces."

The DesignWare Enterprise 10G PHY offers a modular design with a highly configurable physical coding sub-layer (PCS) capable of bifurcation and aggregation. Its analog front-end includes multi-tap decision feedback equalization (DFE) and continuous time linear equalization (CTLE), which enhance signal integrity in high throughput communication channels. The DesignWare Enterprise 10G PHY is optimized for area, power and width to ease integration into the rest of the SoC.

The Enterprise 10G PHY is part of Synopsys' complete PCI Express 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. The PHY's support for 10GBASE-KR includes physical medium attachment (PMA), auto negotiation (AN), PCS, forward error correction (FEC) and energy-efficient Ethernet (EEE). Providing comprehensive 10GBASE-KR support, including the optional EEE and FEC features, enables SoC designers to single-source IP solutions to help ensure interoperability while reducing risk and time-to-market.

"From the start, we designed the DesignWare Enterprise 10G PHY to enable a flexible range of implementations with scalable data rates, support all major networking and computing protocols, and be available at multiple leading foundries," said John Koeter, VP of marketing for IP and systems at Synopsys. "Synopsys' complete PCI Express 3.0 and 10G Ethernet IP solutions enable design teams to integrate ultra-high data throughput functionality into their devices with less risk and without compromising time-to-market."