S2C's quad Virtex-7 2000T 3D IC rapid ASIC prototyping platform optimized for design partitioning

USA: S2C Inc. announced the addition of the newest prototyping platform, Quad V7, to its V7 TAI logic module series, a new generation of SoC/ASIC prototyping hardware based on Xilinx’s Virtex-7 2000T All Programmable 3D ICs.

S2C’s V7 TAI Logic Module series use up to 9 Virtex-7 2000T devices on a single board to make SoC/ASIC prototyping a productive experience for designs of any size from 20 million up to 180 million ASIC gates.

S2C has integrated Xilinx’s Vivado Design Suite in its prototype creation software flow and ChipScope Pro tools in its debug software for accelerated design productivity. In addition, the Quad V7 TAI Logic Module hardware is designed to run high-frequency pin-multiplexing through LVDS interconnection bus to fit designs when partitioned to multiple FPGAs.

“Xilinx’s Virtex-7 2000T All Programmable 3D ICs with their Stacked Silicon Interconnect (SSI) technology are changing the landscape of SoC/ASIC prototyping by enabling advanced system integration capabilities. SSI technology allows multiple die to be combined in a single package to deliver almost three times more logic, memory, serial transceivers, and processing elements than previously available FPGAs,” noted Mon-Ren Chene, chairman and CTO of S2C.

“Rapid FPGA-based prototyping has become a critical step for a successful SoC product launch but was not a viable option when design sizes were extremely large. With four Virtex-7 2000T All Programmable 3D ICs on a single SoC/ASIC prototyping platform, designers can now fit a fairly large design such as an SoC with multi ARM-A15 Cores and multi GPU cores. Traditionally, complex SoC verification has been performed by using expensive emulators that run only at a small fraction of real clock speed, making software development painful.

“S2C’s Quad V7 TAI Logic Modules now allows designers to deploy multiple SoC/ASIC prototypes for both hardware verification and early software development, so the overall SoC design cycle can be greatly reduced. On the technical aspect, we have designed the interconnections between the four All Programmable devices to run large number of LVDS pairs synchronously at over 800MHz. With dedicated LVDS Pin-Multiplexing reference clocks and reset circuits, almost any design can be partitioned easily to our Quad V7 TAI logic module.”

“We are pleased to see S2C among the first few vendors in the Alliance Program ecosystem to offer an ASIC prototyping system based on the world’s largest All Programmable device," noted Dave Tokic, senior director, Partner Ecosystems and Alliances at Xilinx. “S2C has a long history of providing value to the ASIC prototyping community through Xilinx-based rapid prototyping boards leveraging Virtex-6, Virtex-5, Virtex-4 and Virtex-II-Pro FPGA families.”

LVDS pin-multiplexing interconnection support
S2C’s Quad V7 TAI logic module is architected to run pin-multiplexing using LVDS pairs at high-frequency. Users can use either third party partition tools or optional S2C TAI Player Pro software to map a design to the four Virtex-7 2000T devices.

• Supports 80+ pairs length-matched LVDS bus between any two FPGAs optimized for LVDS pin-multiplexing.
• Supports 10,000+ design interconnections between any two FPGAs with LVDS bus running at 800MHz+.
• On-board high-quality programmable LVDS pin-multiplexing clock source.
• Dedicated LVDS pin-multiplexing reference clocks without consuming user resource and dedicated reset button for initializing pin-multiplexing before user design starts.