New release of Cadence Incisive platform doubles productivity of SoC verification

USA: Cadence Design Systems Inc. has introduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release.

Incisive 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today’s complex intellectual property (IP) and SoCs.

For IP block-to-chip verification, enhancements include:
* Doubled performance from the simulator engine.
* Improved debug capabilities with the recently introduced Incisive Debug Analyzer.
* Automated Register Validation App that replaces hundreds of functional tests with a single formal analysis run.
* Simplified coverage data analysis with the new Incisive Metrics Center feature.

At the SoC level, Incisive 12.2 has greater capacity for longer running simulations, including those incorporating low-power and mixed-signal designs.

For SoC verification, enhancements include:
* An enhanced low-power algorithm in the simulator that delivers a 2x improvement in elaboration time. The new Incisive technology accurately models shutdown and recovery in low-power designs.
* An integrated digital-centric mixed-signal solution that uses real number models (RNM), resulting in simulation speed increases of over 300x using wreal or SystemVerilog-RNM types.
* Accelerated block and toggle coverage supported in Palladium XP Simulation Acceleration, reducing test time from hours to minutes.

"Performance, scalability, and efficiency define our high-density switches," said Fred Homewood, CTO and founder of Gnodal Ltd, which plans to deploy the Incisive 12.2 release to its team in 2013. “The Incisive Platform and support team embodies these qualities, leading us to substantially increase our Incisive Enterprise Simulator licenses and deploy the Incisive Enterprise Manager and Incisive SimVision debug. We are implementing the metric-driven verification methodology and will use its automated verification planning capability to demonstrate our development productivity to our customers.”

“Some of our customers are building 200 million-gate SoCs—even larger—at advanced nodes,” said Chi-Ping Hsu, senior VP, Silicon Realization Group at Cadence. “The successful verification of these designs is critical, and it requires the coordination of distributed worldwide teams. Unmatched in the breadth of its technology, Incisive 12.2 provides the productivity improvements these teams need to bring their designs to market fast and at high quality.”

The new Incisive release integrates with Cadence verification IP for SoC verification, the Cadence Virtual System Platform for system verification, and the Palladium XP for acceleration which includes the ability to hot-swap between software-based simulation and hardware-based acceleration.