Real Intent delivers next release of Meridian Constraints for advanced sign-off of SoC designs

USA: Real Intent Inc., a leading provider of EDA advanced sign-off verification solutions, has announced the next release of its Meridian Constraints product for comprehensive design constraint management.

This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent’s product leadership in delivering what the company believes are the industry’s fastest-performance and highest-capacity RT-level verification tools.

New features include:
* Constraints equivalency checks for top-level versus block-level of design to ensure that block-level constraints have been aggregated correctly in the complete design, or that constraints are correctly propagated downward for individual block verification.

* An enhanced timing exceptions verification engine with greater speed and coverage.

* Significant enhancements to the SystemVerilog support and associated error handling.

* Verdi3 integration - the industry-leading debug platform from Synopsys (formerly SpringSoft).

Sarath Kirihennedige, senior manager of product engineering at Real Intent, said: “Designers need to write SDC constraints based on timing goals for new IP and merge these with SDC constraints from existing or imported IP. Unfortunately, until now they had to rely on spreadsheets and manual methods to organize this data.

"Meridian Constraints provides the design automation software to meet the needs of design teams to create, manage, and verify all of the SDC. It ensures the SDC completely covers the design, correctly matches the functional and timing goals and is consistent between different blocks and levels in the design. Having correct and complete constraints and associated clock definitions ensures timing goals are met. It enables correct clock domain crossing analysis, resulting in ultimate confidence for users, and successful low-power and X-verification flows.”

Meridian Constraints offers high-performance constraint validation, constraints template generation, coverage analysis, equivalence checking and timing exception verification capabilities for timing constraints employed across all phases of the synthesis and implementation flow. Real Intent believes no other product delivers such comprehensive SDC management and verification capabilities.