GENEVA, SWITZERLAND: An innovative IC from STMicroelectronics will enable compact digital cameras and cameraphones to satisfy demands for increased power from the built-in flash unit while supporting more sophisticated user controls.
ST’s new chip, the STCF04, is an integrated camera flash and torch controller that raises the maximum power of an LED flash module from a few Watts, typical of today’s designs, to over 40 Watts, producing the brightness equivalent to an outdoor security floodlight. The new device also provides extra flash and torch brightness controls, with eight user-selectable levels for the flash and 12 for the torch, as well as a light-sensor input. Flash and torch safety timers, temperature sensing and short-circuit protection features are also built in.
The STCF04 is used in a unique configuration combining a supercapacitor, a discrete high-current MOSFET switch and high-power white LEDs, and is ideal for use in emergency high-intensity flashing lights as well as camera and cameraphone applications.
The discrete MOSFET is the key to the STCF04’s power advantage over other controllers that usually integrate a MOSFET of lower rating on the chip. Its extra power enables designers to provide the higher quantities of light energy required by today’s high-Mpixel camera sensors by specifying an LED flash unit rather than a conventional high-power xenon flash, thereby gaining the advantage of a compact and simplified design.
Since ST began sampling the STCF04, two major partners – Murata which is leading producer of supercapacitors (MURATA) and OSRAM which is a top-tier supplier of flash modules for leading smartphone platforms have begun using the device to showcase the best capabilities of their latest products.
Major features of STCF04:
• Maximum flash power >40W.
• 1 x 320mA torch current.
• 100mA privacy indicator red LED output; 12 adjustment steps.
• I2C bus with selectable address.
• Temperature sensing, short-circuit, over-voltage and flash/torch timer safety features.
Available in the 25-bump 3 x 3mm TFBGA package, the STCF04 is currently sampling. Full production is planned at the end of Q1 2012 priced at $2.00 for orders of 1,000 pieces. Alternative pricing options may be available for higher quantities.
Tuesday, January 31, 2012
e-con Systems announces camera adapter board
CHENNAI, INDIA: e-con Systems Inc., a leading embedded design services company specializing in development of advanced camera solutions and services announced its camera adapter board e-CAMNT_35x_GSTIX to support analog camera interface for Gumstix Overo COMs.
e-con Systems, e-CAMNT_35x_GSTIXadaptor board can be used as a plug-n- play to interface NTSC/PAL camera. Along with the adapter daughter card, e-con systems also provide drivers for Linux. This Adapter board shall have support for S-Video IN and CVBS IN.
Ashok Babu, president, e-con Systems, said: “The e-CAMNT_35x_GSTIX is aimed at allowing our customers to interface the analog video sources such as NTSC/PAL cameras, analog thermal cameras, analog surveillance cameras, and other NTSC/PAL compatible video sources on OMAP35x/DM37x based Computer-on-Modules from Gumstix.“
e-con Systems, e-CAMNT_35x_GSTIXadaptor board can be used as a plug-n- play to interface NTSC/PAL camera. Along with the adapter daughter card, e-con systems also provide drivers for Linux. This Adapter board shall have support for S-Video IN and CVBS IN.
Ashok Babu, president, e-con Systems, said: “The e-CAMNT_35x_GSTIX is aimed at allowing our customers to interface the analog video sources such as NTSC/PAL cameras, analog thermal cameras, analog surveillance cameras, and other NTSC/PAL compatible video sources on OMAP35x/DM37x based Computer-on-Modules from Gumstix.“
Xilinx launches first design platforms for accelerating 7 series FPGA design productivity and system integration
SAN JOSE, USA: Xilinx Inc. has launched its first Targeted Design Platforms for accelerating systems development and integration with its 28nm 7 series Field-Programmable Gate Arrays (FPGAs).
Xilinx's Targeted Design Platform approach to FPGA system design and integration provides the industry's most comprehensive development kits – complete with boards, ISE Design Suite tools, IP cores, reference designs and FPGA Mezzanine Card (FMC) support – so designers can begin applications development immediately.
At DesignCon 2012, attendees can visit Xilinx at booth #732 to see the new Virtex-7 FPGA VC707 Evaluation Kit, the Kintex-7 FPGA KC705 Evaluation Kit, and the Kintex-7 FPGA DSP Kit with high-speed analog built with Avnet Electronics Marketing.
These kits will showcase applications featuring low power, FMC migration, high-speed connectivity, and advanced Digital Signal Processing (DSP) performance. Xilinx's booth demonstrations will also showcase Xilinx's Agile Mixed Signal (AMS) analog interface capabilities, now available in all its 28nm devices for enabling general purpose analog integration.
"Xilinx's 7 series families take FPGA technology further into SoC applications that were never possible before without costly and time-consuming ASIC or ASSP development," said Vin Ratford, senior VP, World Wide Marketing, Xilinx. "Xilinx is executing a record-breaking rollout of its 28nm generation, which means customers now have access to base and domain platforms as well as a range of ecosystem offerings for evaluating, developing and deploying systems that take advantage of the low-power and flexibility 7 series FPGAs bring to the table."
Since the first Kintex-7 devices were shipped to customers in March 2011, Xilinx has commenced the roll out of its Kintex-325T, Virtex-485T, Virtex-2000T FPGAs and Zynq-7020 Extensible Processing Platform. The three new kits are the first among nearly 40 to be delivered by Xilinx and/or ecosystem members supporting embedded and high-speed connectivity applications, as well as markets such as automotive, broadcast, consumer, industrial and communications.
Reference designs that come with each kit give both new and experienced FPGA users ideal starting points for getting designs completed quickly while achieving the best performance, lowest power, highest bandwidth and most feature-rich utilization of Xilinx FPGAs.
Xilinx's Targeted Design Platform approach to FPGA system design and integration provides the industry's most comprehensive development kits – complete with boards, ISE Design Suite tools, IP cores, reference designs and FPGA Mezzanine Card (FMC) support – so designers can begin applications development immediately.
At DesignCon 2012, attendees can visit Xilinx at booth #732 to see the new Virtex-7 FPGA VC707 Evaluation Kit, the Kintex-7 FPGA KC705 Evaluation Kit, and the Kintex-7 FPGA DSP Kit with high-speed analog built with Avnet Electronics Marketing.
These kits will showcase applications featuring low power, FMC migration, high-speed connectivity, and advanced Digital Signal Processing (DSP) performance. Xilinx's booth demonstrations will also showcase Xilinx's Agile Mixed Signal (AMS) analog interface capabilities, now available in all its 28nm devices for enabling general purpose analog integration.
"Xilinx's 7 series families take FPGA technology further into SoC applications that were never possible before without costly and time-consuming ASIC or ASSP development," said Vin Ratford, senior VP, World Wide Marketing, Xilinx. "Xilinx is executing a record-breaking rollout of its 28nm generation, which means customers now have access to base and domain platforms as well as a range of ecosystem offerings for evaluating, developing and deploying systems that take advantage of the low-power and flexibility 7 series FPGAs bring to the table."
Since the first Kintex-7 devices were shipped to customers in March 2011, Xilinx has commenced the roll out of its Kintex-325T, Virtex-485T, Virtex-2000T FPGAs and Zynq-7020 Extensible Processing Platform. The three new kits are the first among nearly 40 to be delivered by Xilinx and/or ecosystem members supporting embedded and high-speed connectivity applications, as well as markets such as automotive, broadcast, consumer, industrial and communications.
Reference designs that come with each kit give both new and experienced FPGA users ideal starting points for getting designs completed quickly while achieving the best performance, lowest power, highest bandwidth and most feature-rich utilization of Xilinx FPGAs.
Rightware releases Basemark CL for multi-core benchmarking
ESPOO, FINLAND: Rightware, the leader in 3D user interface (UI) technologies and the provider of world’s most widely adopted benchmarking software, announced the public availability of Basemark CL, effective immediately.
This OpenCL (Open Computing Language) benchmark product provides diverse performance measurement capabilities for device manufacturers, semiconductor companies and their ecosystem to test and optimize OpenCL implementations. The version launched today features tests targeted for desktop computers. An embedded profile version of the benchmark will be published at a later stage.
OpenCL by Khronos Group is the first open, royalty-free standard for parallel programming of modern processors found in personal computers, servers and embedded devices. Proper use of OpenCL can greatly improve speed and responsiveness of applications in numerous categories from gaming and entertainment to scientific and medical software.
Within these applications, OpenCL makes it possible to leverage the processing power of Central Processing Units (CPUs), Graphic Processing Units (GPUs) and other processing units for general purpose computation. By utilizing an efficient low-level programming interface, OpenCL will form the foundation layer of a parallel computing ecosystem of platform-independent tools, middleware and applications.
Basemark CL features workloads that stress the OpenCL implementation in a realistic way, therefore yielding performance measurement data that is objective and relevant. With the help of OpenCL, it is possible to improve games, applications and user interfaces for instance by including physics-based animations and game-like elements.
This OpenCL (Open Computing Language) benchmark product provides diverse performance measurement capabilities for device manufacturers, semiconductor companies and their ecosystem to test and optimize OpenCL implementations. The version launched today features tests targeted for desktop computers. An embedded profile version of the benchmark will be published at a later stage.
OpenCL by Khronos Group is the first open, royalty-free standard for parallel programming of modern processors found in personal computers, servers and embedded devices. Proper use of OpenCL can greatly improve speed and responsiveness of applications in numerous categories from gaming and entertainment to scientific and medical software.
Within these applications, OpenCL makes it possible to leverage the processing power of Central Processing Units (CPUs), Graphic Processing Units (GPUs) and other processing units for general purpose computation. By utilizing an efficient low-level programming interface, OpenCL will form the foundation layer of a parallel computing ecosystem of platform-independent tools, middleware and applications.
Basemark CL features workloads that stress the OpenCL implementation in a realistic way, therefore yielding performance measurement data that is objective and relevant. With the help of OpenCL, it is possible to improve games, applications and user interfaces for instance by including physics-based animations and game-like elements.
Semiconductor industry revenue to endure slow growth in 2012
EL SEGUNDO, USA: With global economic prospects remaining uncertain and semiconductor inventory not moving quickly enough to stimulate new production, the worldwide chip market is expected to suffer a slow year in 2012 marked by sluggish growth.
Semiconductor industry revenue in 2012 is expected to reach $323.2 billion, up a slight 3.3 percent from last year’s revenue of $312.8 billion, according to an IHS iSuppli Global Manufacturing Market Tracker report.
While expansion this year is expected to be better than the paltry 1.25 percent increase of 2011, the overall picture could brighten considerably if the United States and the rest of the world recover in 2013. Under such a scenario, growth from 2013 to 2015 will average between a more encouraging 6.6 to 7.9 percent, as shown in the figure, with total semiconductor revenue by 2015 rising to some $397.7 billion.
Source: IHS iSuppli, USA.
“Much of the weak performance in both 2011 and this year can be attributed to external circumstances over which the semiconductor industry has no control—the ambiguous state of the global economy, along with assorted troubles in the world’s major markets of the United States, Europe, Japan and China,” said Len Jelinek, director and chief analyst of semiconductor manufacturing research at IHS. “And because the world economy is not in a strong-enough position to drive growth, the semiconductor business is coming under pressure.”
Consumer spending is also a key factor determining conditions in the chip market. Although consumer spending lowered the level of inventory of electronic devices and other items incorporating semiconductors during the 2011 holiday season, the reduction was insufficient to re-energize chip demand to replenish stockpiles.
Worse, a deliberate decrease in manufacturing run rates by companies in the third quarter of 2011 proved unable to bring inventory down to levels that would have fired up additional orders and increased factory run rates. As a result, semiconductor demand for manufacturers will remain depressed until the second quarter of 2012.
Such developments will have a ripple effect throughout the industry. For instance, because factory utilization will not recover until the middle of 2012, the integrated device manufacturers (IDM) that both design and manufacture semiconductors in-house will experience even greater stress to simply maintain the viability of underperforming factories. And with current manufacturing capacity deemed acceptable for meeting demand, most capital expenditures to boost efficiency within the industry likely will be pushed out to 2013.
Memory under siege; wireless to be a winner
The most beleaguered semiconductor segment will be the memory space, especially in dynamic random access memory (DRAM), with revenue projected to decline to 16.1 percent in 2012 on top of a 26.8 percent fall in 2011. And a once-energetic performer in 2011—NAND flash—will see less rosy prospects this year because of additional capacity coming on to meet a surge of demand for the memory in devices like mobile handsets and media tablets.
In contrast, a strong market revenue driver this year will be the wireless communication segment, spurred by media tablets, smartphones and industrial electronics. For the semiconductor industry to revitalize, however, it is imperative that the core PC and peripheral markets experience a significant increase in demand, IHS believes.
The first half of 2012 is almost certain to be a challenging period for the industry, with negative growth being forecast for the historically slow first-quarter season. The industry will begin to rebound in the second quarter and then go on to a strong third quarter, as is normal for the business.
Foundries dedicated to manufacturing semiconductors as their main activity will continue to outperform the industry, while IDMs will have lower growth, especially as they have abdicated manufacturing in leading-edge technology—where the high margins are—to the foundries. The advice is for IDMs not to sit by idly and allow fabless or foundry companies to control leading-edge design or production on their own.
Otherwise, they risk consolidation, which would have the unintended effect of providing rival foundries with even more opportunities for additional growth.
Source: IHS iSuppli, USA.
Semiconductor industry revenue in 2012 is expected to reach $323.2 billion, up a slight 3.3 percent from last year’s revenue of $312.8 billion, according to an IHS iSuppli Global Manufacturing Market Tracker report.
While expansion this year is expected to be better than the paltry 1.25 percent increase of 2011, the overall picture could brighten considerably if the United States and the rest of the world recover in 2013. Under such a scenario, growth from 2013 to 2015 will average between a more encouraging 6.6 to 7.9 percent, as shown in the figure, with total semiconductor revenue by 2015 rising to some $397.7 billion.
Source: IHS iSuppli, USA.“Much of the weak performance in both 2011 and this year can be attributed to external circumstances over which the semiconductor industry has no control—the ambiguous state of the global economy, along with assorted troubles in the world’s major markets of the United States, Europe, Japan and China,” said Len Jelinek, director and chief analyst of semiconductor manufacturing research at IHS. “And because the world economy is not in a strong-enough position to drive growth, the semiconductor business is coming under pressure.”
Consumer spending is also a key factor determining conditions in the chip market. Although consumer spending lowered the level of inventory of electronic devices and other items incorporating semiconductors during the 2011 holiday season, the reduction was insufficient to re-energize chip demand to replenish stockpiles.
Worse, a deliberate decrease in manufacturing run rates by companies in the third quarter of 2011 proved unable to bring inventory down to levels that would have fired up additional orders and increased factory run rates. As a result, semiconductor demand for manufacturers will remain depressed until the second quarter of 2012.
Such developments will have a ripple effect throughout the industry. For instance, because factory utilization will not recover until the middle of 2012, the integrated device manufacturers (IDM) that both design and manufacture semiconductors in-house will experience even greater stress to simply maintain the viability of underperforming factories. And with current manufacturing capacity deemed acceptable for meeting demand, most capital expenditures to boost efficiency within the industry likely will be pushed out to 2013.
Memory under siege; wireless to be a winner
The most beleaguered semiconductor segment will be the memory space, especially in dynamic random access memory (DRAM), with revenue projected to decline to 16.1 percent in 2012 on top of a 26.8 percent fall in 2011. And a once-energetic performer in 2011—NAND flash—will see less rosy prospects this year because of additional capacity coming on to meet a surge of demand for the memory in devices like mobile handsets and media tablets.
In contrast, a strong market revenue driver this year will be the wireless communication segment, spurred by media tablets, smartphones and industrial electronics. For the semiconductor industry to revitalize, however, it is imperative that the core PC and peripheral markets experience a significant increase in demand, IHS believes.
The first half of 2012 is almost certain to be a challenging period for the industry, with negative growth being forecast for the historically slow first-quarter season. The industry will begin to rebound in the second quarter and then go on to a strong third quarter, as is normal for the business.
Foundries dedicated to manufacturing semiconductors as their main activity will continue to outperform the industry, while IDMs will have lower growth, especially as they have abdicated manufacturing in leading-edge technology—where the high margins are—to the foundries. The advice is for IDMs not to sit by idly and allow fabless or foundry companies to control leading-edge design or production on their own.
Otherwise, they risk consolidation, which would have the unintended effect of providing rival foundries with even more opportunities for additional growth.
Source: IHS iSuppli, USA.
TI unveils world's smallest half duplex (HDX) RFID mini-transponders
DALLAS, USA: Raising the standard in half duplex (HDX) transponder technology, Texas Instruments Inc. (TI) announced the world's smallest half-duplex radio frequency identification (RFID) mini-transponders that enable customers to embed tags into smaller objects across a broader range of applications.
The 12mm TRPGR30TGC and TRPGP40TGC glass encapsulated mini-transponders are ready-to-use and 100 percent backwards compatible with all of TI's RFID software and readers including power modules, control modules and micro readers. The TRPGP40TGC is programmable according to ISO 11784 / 11785 global livestock ID standards so customers can create compatible products that can be read by 134.2 kHz ISO-compliant receivers/infrastructure worldwide.
The mini-transponders are durable enough for use in applications including tool, medical instrument, package and inventory tracking and safe enough for use in fish and livestock tracking and pet identification and are expected to work for up to 30 years.
TI's industry-leading HDX technology, hermetically encapsulated in the world's first 12mm glass transponder, gives customers the upper hand in creating RFID applications. The read range extends up to 20 inches (50 centimeters) and allows for easier tag spotting for fish tracking in fresh water and even in salt water environments where FDX technology completely fails. TI's HDX technology has high resistance to noise through frequency-shift keying (FSK) modulation and consistent performance through parametric testing and electronic resonance tuning performed on each mini-transponder throughout the production cycle.
The 12mm TRPGR30TGC and TRPGP40TGC glass encapsulated mini-transponders are ready-to-use and 100 percent backwards compatible with all of TI's RFID software and readers including power modules, control modules and micro readers. The TRPGP40TGC is programmable according to ISO 11784 / 11785 global livestock ID standards so customers can create compatible products that can be read by 134.2 kHz ISO-compliant receivers/infrastructure worldwide.
The mini-transponders are durable enough for use in applications including tool, medical instrument, package and inventory tracking and safe enough for use in fish and livestock tracking and pet identification and are expected to work for up to 30 years.
TI's industry-leading HDX technology, hermetically encapsulated in the world's first 12mm glass transponder, gives customers the upper hand in creating RFID applications. The read range extends up to 20 inches (50 centimeters) and allows for easier tag spotting for fish tracking in fresh water and even in salt water environments where FDX technology completely fails. TI's HDX technology has high resistance to noise through frequency-shift keying (FSK) modulation and consistent performance through parametric testing and electronic resonance tuning performed on each mini-transponder throughout the production cycle.
Microchip and Digilent unveil PIC32-based Cerebot development boards with chipKIT prototyping capabilities
CHANDLER, USA: Microchip Technology Inc. and Digilent Inc. announced several new 32-bit PIC32 microcontroller (MCU)-based Cerebot development boards with prototyping capabilities for the Arduino compatible chipKIT development platform.
The Cerebot MX3cK, Cerebot MX4cK and Cerebot MX7cK (MX3/4/7) boards provide a single, general-purpose development platform for users to develop a wide range of 32-bit MCU applications using the free, Arduino-compatible chipKIT IDE—called the Multi-Platform IDE, or “MPIDE.”
Users can later migrate to development tools that are more widely recognized in the industry, such as Microchip’s MPLAB X IDE and MPLAB C Compiler for PIC32 MCUs. The Cerebot MX3/4/7 boards break free from the traditional Arduino form factor, providing flexible pin access and connectivity with Digilent’s line of Pmod™ Peripheral Modules.
Introduced in May 2011, the PIC32 MCU-based chipKIT Uno32 and Max32 boards enable hobbyists and academics to easily and inexpensively add electronics to their projects, even if they don’t have an engineering background. The new Cerebot “cK” development boards include hardware that enables connectivity to the MPIDE, so users can develop with chipKIT via a bootloader application. Microchip’s PICkit 3 debugger/programmer can be used with the Cerebot MX3cK.
The Cerebot MX4cK and MX7cK boards feature an integrated programmer/debugger. These boards are each populated with multiple connectors for Digilent’s numerous Pmod I/O interface boards, which provide ready-made interface circuitry for LCD, wireless, motor-control, sensor and many other applications, minimizing the need for users to create original circuitry.
The Cerebot MX3cK, Cerebot MX4cK and Cerebot MX7cK (MX3/4/7) boards provide a single, general-purpose development platform for users to develop a wide range of 32-bit MCU applications using the free, Arduino-compatible chipKIT IDE—called the Multi-Platform IDE, or “MPIDE.”
Users can later migrate to development tools that are more widely recognized in the industry, such as Microchip’s MPLAB X IDE and MPLAB C Compiler for PIC32 MCUs. The Cerebot MX3/4/7 boards break free from the traditional Arduino form factor, providing flexible pin access and connectivity with Digilent’s line of Pmod™ Peripheral Modules.
Introduced in May 2011, the PIC32 MCU-based chipKIT Uno32 and Max32 boards enable hobbyists and academics to easily and inexpensively add electronics to their projects, even if they don’t have an engineering background. The new Cerebot “cK” development boards include hardware that enables connectivity to the MPIDE, so users can develop with chipKIT via a bootloader application. Microchip’s PICkit 3 debugger/programmer can be used with the Cerebot MX3cK.
The Cerebot MX4cK and MX7cK boards feature an integrated programmer/debugger. These boards are each populated with multiple connectors for Digilent’s numerous Pmod I/O interface boards, which provide ready-made interface circuitry for LCD, wireless, motor-control, sensor and many other applications, minimizing the need for users to create original circuitry.
LDRA tool suite directly integrates with Altera’s Nios II embedded design suite
MONKS FERRY, UK: LDRA, the leader in standards compliance, automated software verification, source code analysis and test tools, has extended the LDRA tool suite to support direct integration with Altera’s Embedded Design Suite (EDS) for Nios II soft core processors.
In the past, these processors lacked sufficient CPU and memory to be used in automotive, medical, industrial and avionics environments. However, with the advent of the Nios II family, entire chip sets can be replaced with an Altera FPGA, making them ideal for applications that must be certified. LDRA’s integration ensures that standards such as DO-178B/C, MISRA and IEC 61508 can be verified and validated directly when using these soft core processors.
To achieve integration, LDRA takes advantage of Nios II tool chain characteristics. Using the GNU GCC tool chain and Eclipse IDE to program the Nios II, developers can take advantage of soft core processors previously only available on ASICs with custom chip sets. LDRA leverages the host I/O capability of the GCC tool chain to create unit and system tests that transfer data back into the host processor seamlessly. Within the Eclipse environment, tests can be automated to load and execute, saving time during verification.
“Achieving certification is no easy task,” confirmed Ian Hennell, LDRA Operations director. “The LDRA tool suite features templates tailored to specific industry and programming standards. These are delivered pre-populated with standard requirements, simplifying compliance for developers. LDRA’s verification strengths combined with a cost-reduced platform such as Nios II lower the cost of embedded systems in industries such as automotive, medical, and avionics, where such applications are ideal.”
By using the LDRA tool suite, companies gain the validation tools necessary to ensure that a software application produced on a Nios II platform is certifiable. Since FPGA-based soft core processors achieve significant cost savings over custom hard core processors both in actual cost and the reduced amount of board design, the LDRA integration provides increased market opportunities for mission- and safety-critical developers wanting to take advantage of this Altera processor family.
The LDRA tool suite offers independent verification support across the full development lifecycle from certification objectives of standards, such as DO-178B/C, IEC 61508, ISO 26262, and IEC 62304, to requirements, code and target testing. LDRA’s unique ability to provide bidirectional traceability from requirements through model, code and tests allows development teams both to validate programming standards and automate their certification process.
In the past, these processors lacked sufficient CPU and memory to be used in automotive, medical, industrial and avionics environments. However, with the advent of the Nios II family, entire chip sets can be replaced with an Altera FPGA, making them ideal for applications that must be certified. LDRA’s integration ensures that standards such as DO-178B/C, MISRA and IEC 61508 can be verified and validated directly when using these soft core processors.
To achieve integration, LDRA takes advantage of Nios II tool chain characteristics. Using the GNU GCC tool chain and Eclipse IDE to program the Nios II, developers can take advantage of soft core processors previously only available on ASICs with custom chip sets. LDRA leverages the host I/O capability of the GCC tool chain to create unit and system tests that transfer data back into the host processor seamlessly. Within the Eclipse environment, tests can be automated to load and execute, saving time during verification.
“Achieving certification is no easy task,” confirmed Ian Hennell, LDRA Operations director. “The LDRA tool suite features templates tailored to specific industry and programming standards. These are delivered pre-populated with standard requirements, simplifying compliance for developers. LDRA’s verification strengths combined with a cost-reduced platform such as Nios II lower the cost of embedded systems in industries such as automotive, medical, and avionics, where such applications are ideal.”
By using the LDRA tool suite, companies gain the validation tools necessary to ensure that a software application produced on a Nios II platform is certifiable. Since FPGA-based soft core processors achieve significant cost savings over custom hard core processors both in actual cost and the reduced amount of board design, the LDRA integration provides increased market opportunities for mission- and safety-critical developers wanting to take advantage of this Altera processor family.
The LDRA tool suite offers independent verification support across the full development lifecycle from certification objectives of standards, such as DO-178B/C, IEC 61508, ISO 26262, and IEC 62304, to requirements, code and target testing. LDRA’s unique ability to provide bidirectional traceability from requirements through model, code and tests allows development teams both to validate programming standards and automate their certification process.
Touchstone launches video channel
MILPITAS, USA: Touchstone Semiconductor, a developer of high-performance analog integrated circuit solutions, has launched the new Touchstone Video Channel featuring application videos to help design engineers in applying Touchstone’s analog ICs.
The channel will host a mix of videos by Touchstone Applications and Design Engineering team members and industry experts. Touchstone’s design engineers will host upcoming “The IC Designers’ Corner” where they discuss the features and benefits of ICs they have designed. In addition, Touchstone’s industry experts will present design ideas on a wide range of applications targeting industrial and process control, energy harvesting, medical devices, hand-held and portable instrumentation, consumer electronics, and power management.
“The Touchstone videos give engineers a peek at how we design our products and address potential applications, especially those requiring high performance while operating from low power or low voltage sources,” said Adolfo Garcia, VP, Applications and Marketing, Touchstone Semiconductor. “The videos are short, to the point and chock full of useful information presented by engineers to engineers.”
The channel will host a mix of videos by Touchstone Applications and Design Engineering team members and industry experts. Touchstone’s design engineers will host upcoming “The IC Designers’ Corner” where they discuss the features and benefits of ICs they have designed. In addition, Touchstone’s industry experts will present design ideas on a wide range of applications targeting industrial and process control, energy harvesting, medical devices, hand-held and portable instrumentation, consumer electronics, and power management.
“The Touchstone videos give engineers a peek at how we design our products and address potential applications, especially those requiring high performance while operating from low power or low voltage sources,” said Adolfo Garcia, VP, Applications and Marketing, Touchstone Semiconductor. “The videos are short, to the point and chock full of useful information presented by engineers to engineers.”
Analog Devices’ FMC boards support Xilinx’s FPGA Targeted Design Platforms
DesignCon 2012, NORWOOD, USA: Analog Devices Inc. (ADI) introduced two data converter FMC boards (FPGA mezzanine cards) that connect to Xilinx Inc.’s new 28nm 7 series FPGA (field programmable gate array) evaluation kits.
ADI’s high-speed AD9739A D/A converter and AD9467 A/D converter FMC boards support multiple generations of Xilinx kits -- including the company’s new Kintex-7 FPGA evaluation kits Xilinx announced today. The new Analog Devices FMC boards include all of the HDL (hardware description language) code and device drivers needed for designers to engage in rapid prototyping and reduce development time and risk. Both products are being demonstrated at the DesignCon 2012 trade show in Santa Clara, Calif., in the Xilinx booth (#732).
"The availability of low cost commercial off the shelf hardware, such as the AD9739A FMC board, and the new Kintex-7 development boards, allows our customers to quickly prototype and evaluate many of the IP Cores which we offer," said Jean-Claude Basset, technical director/manager, MVD Cores, a Certified Member of the Xilinx Alliance Program. "We have verified our digital RF up converter IP cores with the AD9739A FMC board and Xilinx's Virtex-6, Kintex-7 and Spartan-6 boards and recommend that our customers use this hardware to evaluate our IP Cores."
ADI’s high-speed AD9739A D/A converter and AD9467 A/D converter FMC boards support multiple generations of Xilinx kits -- including the company’s new Kintex-7 FPGA evaluation kits Xilinx announced today. The new Analog Devices FMC boards include all of the HDL (hardware description language) code and device drivers needed for designers to engage in rapid prototyping and reduce development time and risk. Both products are being demonstrated at the DesignCon 2012 trade show in Santa Clara, Calif., in the Xilinx booth (#732).
"The availability of low cost commercial off the shelf hardware, such as the AD9739A FMC board, and the new Kintex-7 development boards, allows our customers to quickly prototype and evaluate many of the IP Cores which we offer," said Jean-Claude Basset, technical director/manager, MVD Cores, a Certified Member of the Xilinx Alliance Program. "We have verified our digital RF up converter IP cores with the AD9739A FMC board and Xilinx's Virtex-6, Kintex-7 and Spartan-6 boards and recommend that our customers use this hardware to evaluate our IP Cores."
PMC’s 12Gb/s SAS controllers and expanders set performance and density records for cloud and tiered storage
SUNNYVALE, USA: PMC-Sierra Inc. announced the availability of its 12Gb/s SAS protocol controllers, RAID-on-Chip (RoC) controllers and expanders to enable breakthrough performance and scalability for server and networked storage.
High-performance solid state drives (SSDs) can deliver up to 100 times more I/Os per second (IOPS) than traditional hard disk drives (HDDs), creating the need for a new class of storage controller. PMC’s 12Gb/s SAS controllers are optimized for performance to solve this need and release the full potential of SSDs. With the addition of the industry’s highest port count expanders, PMC’s 12Gb/s solution delivers 40 percent more drive connectivity than competitive solutions, enabling a new generation of scalable tiered storage for corporate and cloud data centers.
“Building on the market leadership of our 6Gb/s SAS products, PMC is pleased to announce the availability of the industry’s leading 12Gb/s controller and expander products,” said Derek Dicker, VP of marketing for PMC’s Enterprise Storage Division. “With the most advanced integration and the highest performance available, our customers can design systems that scale with the exponential growth in storage data at the lowest cost and power.”
Demonstrations of PMC’s Tachyon 12Gb/s SAS controllers have delivered well over two million IOPS with a single 16-port controller running small block sequential reads connected to 6Gb/s SAS drives via PMC SAS expanders. PMC’s controllers provide more than double the performance of competing 12Gb/s SAS controllers, which enables OEM storage solutions to fully harness the capabilities of the latest SSDs and improve the performance of large-scale HDD topologies.
PMC’s 16-port controller provides twice the port density than competitive solutions. Combined with PMC’s 68-port SXP 12G expander, OEMs can double overall storage system capacity, while reducing components and saving board real estate and power. PMC’s expanders have 40 percent more SAS ports and can scale to support double the number of drives than competitive products, enabling customers to build solutions that span from entry-level to high-end markets. 12Gb/s SAS provides the increased throughput needed for these scale-out architectures.
High-performance solid state drives (SSDs) can deliver up to 100 times more I/Os per second (IOPS) than traditional hard disk drives (HDDs), creating the need for a new class of storage controller. PMC’s 12Gb/s SAS controllers are optimized for performance to solve this need and release the full potential of SSDs. With the addition of the industry’s highest port count expanders, PMC’s 12Gb/s solution delivers 40 percent more drive connectivity than competitive solutions, enabling a new generation of scalable tiered storage for corporate and cloud data centers.
“Building on the market leadership of our 6Gb/s SAS products, PMC is pleased to announce the availability of the industry’s leading 12Gb/s controller and expander products,” said Derek Dicker, VP of marketing for PMC’s Enterprise Storage Division. “With the most advanced integration and the highest performance available, our customers can design systems that scale with the exponential growth in storage data at the lowest cost and power.”
Demonstrations of PMC’s Tachyon 12Gb/s SAS controllers have delivered well over two million IOPS with a single 16-port controller running small block sequential reads connected to 6Gb/s SAS drives via PMC SAS expanders. PMC’s controllers provide more than double the performance of competing 12Gb/s SAS controllers, which enables OEM storage solutions to fully harness the capabilities of the latest SSDs and improve the performance of large-scale HDD topologies.
PMC’s 16-port controller provides twice the port density than competitive solutions. Combined with PMC’s 68-port SXP 12G expander, OEMs can double overall storage system capacity, while reducing components and saving board real estate and power. PMC’s expanders have 40 percent more SAS ports and can scale to support double the number of drives than competitive products, enabling customers to build solutions that span from entry-level to high-end markets. 12Gb/s SAS provides the increased throughput needed for these scale-out architectures.
Cortus and SST to exhibit low power IP solutions for SoC design
Embedded World 2012, MONTPELLIER, FRANCE & SUNNYVALE, USA: Cortus S.A., and Silicon Storage Technology (SST) Inc. will be showing their low power IP products for embedded system on chip (SoC) designs at Embedded World 2012 in Nuremberg, Germany. The exhibit will combine Cortus’ silicon efficient, ultra low power 32 bit microcontroller cores with SST’s low power, ultra high endurance embedded flash non-volatile memory (NVM) technology.
Today’s embedded SoC applications such as SIM cards, Near Field Communications (NFC), Bluetooth LE, automotive sensors and smart meters all require a combination of a microcontroller core and flash memory. Such applications require minimising both power dissipation and silicon area. The Cortus APS3 offers the smallest silicon footprint and power dissipation on the market for 32 bit processor cores. SST SuperFlash technology provides a compact, low power embedded flash memory solution with ultra high endurance.
The Embedded World 2012 exhibition runs from the 28th February to 1st March at the Exhibition Centre Nuremberg and is recognised as Europe’s largest industry event for embedded systems. Cortus S.A. and SST will be exhibiting at Embedded World and will be located at Stand 143 in Hall 5.
Cortus offers high performance 32-bit processor cores designed specifically for embedded systems. The APS3 features a tiny silicon footprint (same size as an 8051), very low power consumption, high code density and high performance (up to 1.67 DMIPS/MHz). The ecosystem around the Cortus processors includes a full development environment (for C and C++), commonly used peripherals, bus bridges to ensure easy interfacing to other IP and system support and functions such as cache and memory management units. The APS3 processor core is currently in volume production in a range of products from security applications to ultra low power wireless designs.
SST Superflash memory technology is the most widely licensed flash NVM technology today, and is commonly used in microcontrollers and automotive and smartcard devices. In 2010 alone, over four billion devices worldwide were manufactured using this technology.
Today’s embedded SoC applications such as SIM cards, Near Field Communications (NFC), Bluetooth LE, automotive sensors and smart meters all require a combination of a microcontroller core and flash memory. Such applications require minimising both power dissipation and silicon area. The Cortus APS3 offers the smallest silicon footprint and power dissipation on the market for 32 bit processor cores. SST SuperFlash technology provides a compact, low power embedded flash memory solution with ultra high endurance.
The Embedded World 2012 exhibition runs from the 28th February to 1st March at the Exhibition Centre Nuremberg and is recognised as Europe’s largest industry event for embedded systems. Cortus S.A. and SST will be exhibiting at Embedded World and will be located at Stand 143 in Hall 5.
Cortus offers high performance 32-bit processor cores designed specifically for embedded systems. The APS3 features a tiny silicon footprint (same size as an 8051), very low power consumption, high code density and high performance (up to 1.67 DMIPS/MHz). The ecosystem around the Cortus processors includes a full development environment (for C and C++), commonly used peripherals, bus bridges to ensure easy interfacing to other IP and system support and functions such as cache and memory management units. The APS3 processor core is currently in volume production in a range of products from security applications to ultra low power wireless designs.
SST Superflash memory technology is the most widely licensed flash NVM technology today, and is commonly used in microcontrollers and automotive and smartcard devices. In 2010 alone, over four billion devices worldwide were manufactured using this technology.
2HJan. 4GB contract price rises, DRAM makers’ losses may shrink
TAIWAN: According to DRAMeXchange, a research division of TrendForce, 2H Jan. 2GB DRAM contract price remained flat, with average price at $9.25. However, 4GB deals have already been concluded at a high of $17.25, greater than 1H Jan.’s $17, while the average stayed the same at $16.5.
This is an indication that 4GB module price growth momentum is stronger than that of 2GB modules, and overall concluded transaction price is noticeably headed towards exceeding average price. Based on the US$17.25 price, 2Gb single chip price is approximately $0.9. DRAM makers further along in the 4Gb transition process are enjoying costs of $1.81 per chip.
Basing calculations on the mature 30nm process, production cost just about breaks even. At the current stage, DRAM manufacturers’ actual profitability and process migration progress are highly related, and both the shrinking of process technology and the transition to 4Gb single chip production play key roles in profitability.
In terms of the spot market, as the Chinese New Year holiday has just ended, there have been few concluded deals. Average 2Gb spot price is in the $0.94-0.97 range, gradually closing the gap between spot and contract price. Whether spot price will continue to rise, thereby stimulating a contract price increase as well, will not be clear until further evaluation of Chinese New Year sales.
However, according to TrendForce research, module makers who play an important role in the spot market are planning to slow inventory restocking to deal with possible DRAM price increases, which will provide substantial support for spot price.
DRAM supply price increase brewing, weak market demand remains an uncertainty
DRAM industry oversupply was severe in 2011, causing long-term, weak DRAM prices. Besides the largest Korean manufacturers who stayed profitable, makers were unable to withstand the prolonged losses and had to react by not only lowering capacity utilization rates and attempting to decrease net cash outflow, but lowering this year’s capex figures as well – an indication of the extent of makers’ difficulties.
Benefitting from 4Q11 PC DRAM production cuts that amounted to approximately 20 percent of total capacity, TrendForce expects the DRAM oversupply ratio to improve significantly, decreasing from the original 16 percent to 10 percent, the healthiest figure in the past year. DRAM makers are becoming inflexible in terms of price quotes, as stabilizing and gradually increasing DRAM price is tacitly understood as a shared industry goal.
Many DRAM manufacturers have set a minimum for price quotes, which not only prevents DRAM price from falling further, but encourages buyers to increase purchase volume for each order. Some makers are even actively negotiating with buyers to set shipment volume and price on a quarterly basis. DRAM suppliers are gradually employing more rational policies to deal with price changes, which is expected to have a positive effect on price stability.
However, whether or not the supply-side adjustment is fully effective will depend on support from the demand end. According to TrendForce research, as the market is currently in the slow season and there is a lack of momentum for PC upgrades, total notebook shipment volume is expected to decrease by a considerable 9.7 percent QoQ, likely the lowest quarterly demand for the year.
Furthermore, although the market is bubbling with rumors of impending DRAM price increases, in order to save on key component production cost PC OEMs are not likely to increase content per box – instead, they are turning towards the spot market.
Affected by the decrease in business days in January, concluded transaction volume was as expected, with purchasing volume low. As for February, buyers are still biding their time as they are highly concerned about the demand situation. In light of this, currently DRAM makers are continuing their technology migration efforts, but there has been no news of manufacturers increasing capacity utilization rates to increase production.
Taking both supply and demand into consideration, there is limited possibility of DRAM price exhibiting a V-shaped curve. DRAM makers are all treading thin ice when it comes to product planning, carefully maintaining price and trying to make it through the weak first quarter to the more optimistic second half of the year.
This is an indication that 4GB module price growth momentum is stronger than that of 2GB modules, and overall concluded transaction price is noticeably headed towards exceeding average price. Based on the US$17.25 price, 2Gb single chip price is approximately $0.9. DRAM makers further along in the 4Gb transition process are enjoying costs of $1.81 per chip.
Basing calculations on the mature 30nm process, production cost just about breaks even. At the current stage, DRAM manufacturers’ actual profitability and process migration progress are highly related, and both the shrinking of process technology and the transition to 4Gb single chip production play key roles in profitability.
In terms of the spot market, as the Chinese New Year holiday has just ended, there have been few concluded deals. Average 2Gb spot price is in the $0.94-0.97 range, gradually closing the gap between spot and contract price. Whether spot price will continue to rise, thereby stimulating a contract price increase as well, will not be clear until further evaluation of Chinese New Year sales.
However, according to TrendForce research, module makers who play an important role in the spot market are planning to slow inventory restocking to deal with possible DRAM price increases, which will provide substantial support for spot price.
DRAM supply price increase brewing, weak market demand remains an uncertainty
DRAM industry oversupply was severe in 2011, causing long-term, weak DRAM prices. Besides the largest Korean manufacturers who stayed profitable, makers were unable to withstand the prolonged losses and had to react by not only lowering capacity utilization rates and attempting to decrease net cash outflow, but lowering this year’s capex figures as well – an indication of the extent of makers’ difficulties.
Benefitting from 4Q11 PC DRAM production cuts that amounted to approximately 20 percent of total capacity, TrendForce expects the DRAM oversupply ratio to improve significantly, decreasing from the original 16 percent to 10 percent, the healthiest figure in the past year. DRAM makers are becoming inflexible in terms of price quotes, as stabilizing and gradually increasing DRAM price is tacitly understood as a shared industry goal.
Many DRAM manufacturers have set a minimum for price quotes, which not only prevents DRAM price from falling further, but encourages buyers to increase purchase volume for each order. Some makers are even actively negotiating with buyers to set shipment volume and price on a quarterly basis. DRAM suppliers are gradually employing more rational policies to deal with price changes, which is expected to have a positive effect on price stability.
However, whether or not the supply-side adjustment is fully effective will depend on support from the demand end. According to TrendForce research, as the market is currently in the slow season and there is a lack of momentum for PC upgrades, total notebook shipment volume is expected to decrease by a considerable 9.7 percent QoQ, likely the lowest quarterly demand for the year.
Furthermore, although the market is bubbling with rumors of impending DRAM price increases, in order to save on key component production cost PC OEMs are not likely to increase content per box – instead, they are turning towards the spot market.
Affected by the decrease in business days in January, concluded transaction volume was as expected, with purchasing volume low. As for February, buyers are still biding their time as they are highly concerned about the demand situation. In light of this, currently DRAM makers are continuing their technology migration efforts, but there has been no news of manufacturers increasing capacity utilization rates to increase production.
Taking both supply and demand into consideration, there is limited possibility of DRAM price exhibiting a V-shaped curve. DRAM makers are all treading thin ice when it comes to product planning, carefully maintaining price and trying to make it through the weak first quarter to the more optimistic second half of the year.
TowerJazz and Triune Systems announce nanoSmart products
APEC 2012, NEWPORT BEACH & RICHARDSON, USA: TowerJazz, the global specialty foundry leader, and Triune Systems LLC, an IC design and test development provider, have announced that Triune has developed a proprietary analog/power management technology using the TowerJazz TS35PM process on its state of the art 0.18um based power management platform.
Triune has trademarked this energy saving green technology, called nanoSmart, and is releasing two products currently ramping to volume production showcasing this technology, the TS14001 and TS12001.
Triune’s TS14001 is an ultra-low-power LDO regulator which provides regulated output with best-in-class ultra-low quiescent current losses of 20nA under no-load conditions which helps reduce energy and heat. The TS12001 is an ultra-low-power under voltage load protect switch that utilizes off-active technology. Off-active provides active control of turning off, and then on, the control of the load with only 200pA losses, increasing efficiencies and resulting in less power wasted.
In addition to these two products, several more energy saving products are planned to be launched this year to meet growing market demands. According to IDTechEx, the energy harvesting device market is projected to grow exponentially this decade; 10B+ energy harvesting devices are forecast to ship by 2019 – a 20x increase over ~500 million units that shipped in 2009.
nanoSmart technology has been designed to target portable and low power applications for the consumer, industrial and medical markets as well as energy harvesting systems, off-grid autonomous systems such as solar panels for electricity, and SmartCard applications. Advantages of nanoSmart technology include ultra-low power loss for light load conditions, flexibility to work with a wide range of output loads, and a minimized bill of materials (BOM) while still providing high-efficiency operation.
Triune’s nanoSmart and MPPT-lite technologies have also been leveraged for novel portable solar harvesting solutions through a National Science Foundation small business innovation and research (SBIR) grant award (No. 1113400). In addition, nanoSmart technology can eliminate standby power losses for many systems and extend battery life on portable products. It expands the utility of alternate energy harvesting sources such as micro-solar and enables new autonomous systems.
“We chose to develop this ultra-low power technology for analog and power management applications with TowerJazz because they offered the best process for our needs, and were willing to work with us on differentiated out-of-the-box solutions,” said Ross Teggatz, president of Triune Systems. “Our nanoSmart technology further leverages TowerJazz’s processes to provide truly unique solutions that can virtually eliminate the carbon footprint of any product while in standby mode, and we look forward to developing several new and exciting products around this.”
“TowerJazz continually draws on our customers’ needs to drive our technology offerings. And, the fact that power management experts such as Triune’s engineers chose TowerJazz’s power platform is proof of our technology superiority. Triune has been a valued partner for several years and their inputs have contributed to the best-in-class power management technology we have today. The device performance capability of nanoSmart demonstrates what cooperation and flexibility can achieve in implementing new ideas,” said Dr. Avi Strum, VP and GM of the Specialty Business Unit at TowerJazz.
Triune has trademarked this energy saving green technology, called nanoSmart, and is releasing two products currently ramping to volume production showcasing this technology, the TS14001 and TS12001.
Triune’s TS14001 is an ultra-low-power LDO regulator which provides regulated output with best-in-class ultra-low quiescent current losses of 20nA under no-load conditions which helps reduce energy and heat. The TS12001 is an ultra-low-power under voltage load protect switch that utilizes off-active technology. Off-active provides active control of turning off, and then on, the control of the load with only 200pA losses, increasing efficiencies and resulting in less power wasted.
In addition to these two products, several more energy saving products are planned to be launched this year to meet growing market demands. According to IDTechEx, the energy harvesting device market is projected to grow exponentially this decade; 10B+ energy harvesting devices are forecast to ship by 2019 – a 20x increase over ~500 million units that shipped in 2009.
nanoSmart technology has been designed to target portable and low power applications for the consumer, industrial and medical markets as well as energy harvesting systems, off-grid autonomous systems such as solar panels for electricity, and SmartCard applications. Advantages of nanoSmart technology include ultra-low power loss for light load conditions, flexibility to work with a wide range of output loads, and a minimized bill of materials (BOM) while still providing high-efficiency operation.
Triune’s nanoSmart and MPPT-lite technologies have also been leveraged for novel portable solar harvesting solutions through a National Science Foundation small business innovation and research (SBIR) grant award (No. 1113400). In addition, nanoSmart technology can eliminate standby power losses for many systems and extend battery life on portable products. It expands the utility of alternate energy harvesting sources such as micro-solar and enables new autonomous systems.
“We chose to develop this ultra-low power technology for analog and power management applications with TowerJazz because they offered the best process for our needs, and were willing to work with us on differentiated out-of-the-box solutions,” said Ross Teggatz, president of Triune Systems. “Our nanoSmart technology further leverages TowerJazz’s processes to provide truly unique solutions that can virtually eliminate the carbon footprint of any product while in standby mode, and we look forward to developing several new and exciting products around this.”
“TowerJazz continually draws on our customers’ needs to drive our technology offerings. And, the fact that power management experts such as Triune’s engineers chose TowerJazz’s power platform is proof of our technology superiority. Triune has been a valued partner for several years and their inputs have contributed to the best-in-class power management technology we have today. The device performance capability of nanoSmart demonstrates what cooperation and flexibility can achieve in implementing new ideas,” said Dr. Avi Strum, VP and GM of the Specialty Business Unit at TowerJazz.
Intersil's single and dual channel 14-bit ADCs are industry's fastest with JESD204B serial outputs
MILPITAS, USA: Intersil Corp. has introduced the industry's fastest, lowest power single and dual channel 14-bit analog-to-digital converters with JESD204B serial outputs. These serial output ADCs provide single channel sampling rates up to 500 Megasamples/second and dual channel rates up to 250 Megasamples/second.
The ISLA224S/ISLA214S50 series represent the first ADCs now in production with JESD204B serial outputs. The integrated JESD204B-compatible transmitter offers data rates up to 4.375Gbps per lane, requiring only two lanes to support either the dual channel 14-bit 250Msps converter (one lane per channel) or the single channel 14-bit 500Msps device.
An optional third lane is included in the transmitter to support the maximum sampling rate while operating the serial lanes at less than 3.125Gbps, providing backwards compatibility with the JESD204A standard to support lower cost FPGAs. The JESD204B transmitter also provides deterministic latency between the ADC sample clock and the serialized data stream. This meets the synchronization requirements of multi-channel and I/Q communications systems.
Power consumption for the ISLA224S25 is just 980mW at 250Msps, compared with 1000mW or higher among competitive serial devices with lower sample rates. For the ISLA214S50, power consumption is just 1050mW compared with 2500mW for competing products.
The ADCs feature a compact footprint of just 7x7mm. They are built using Intersil's FemtoCharge technology on a standard CMOS process with the proven core from Intersil's popular ISLA224Pxx series, which delivers best-in-class signal-to-noise ratio (SNR).
The ISLA224S and ISLA214S50 are optimal for high performance data acquisition and broadband communications systems. They are also ideal design choices for high speed medical imaging systems, microwave receivers and radar or satellite antenna array processing, and other high speed applications. Also, the integrated 8b/10b serializer eliminates the need for an external serializing device, simplifying the design of serial-data communications systems.
The ISLA224S/ISLA214S50 series represent the first ADCs now in production with JESD204B serial outputs. The integrated JESD204B-compatible transmitter offers data rates up to 4.375Gbps per lane, requiring only two lanes to support either the dual channel 14-bit 250Msps converter (one lane per channel) or the single channel 14-bit 500Msps device.
An optional third lane is included in the transmitter to support the maximum sampling rate while operating the serial lanes at less than 3.125Gbps, providing backwards compatibility with the JESD204A standard to support lower cost FPGAs. The JESD204B transmitter also provides deterministic latency between the ADC sample clock and the serialized data stream. This meets the synchronization requirements of multi-channel and I/Q communications systems.
Power consumption for the ISLA224S25 is just 980mW at 250Msps, compared with 1000mW or higher among competitive serial devices with lower sample rates. For the ISLA214S50, power consumption is just 1050mW compared with 2500mW for competing products.
The ADCs feature a compact footprint of just 7x7mm. They are built using Intersil's FemtoCharge technology on a standard CMOS process with the proven core from Intersil's popular ISLA224Pxx series, which delivers best-in-class signal-to-noise ratio (SNR).
The ISLA224S and ISLA214S50 are optimal for high performance data acquisition and broadband communications systems. They are also ideal design choices for high speed medical imaging systems, microwave receivers and radar or satellite antenna array processing, and other high speed applications. Also, the integrated 8b/10b serializer eliminates the need for an external serializing device, simplifying the design of serial-data communications systems.
Silicon Labs intros industry’s smallest, lowest power customizable clock ICs
AUSTIN, USA: Silicon Laboratories Inc. has introduced the industry’s smallest and lowest power customizable clock generators. Available in a tiny 1.7 mm-squared package, Silicon Labs’ new Si512xx clock generator family offers up to 60 percent lower power than competing solutions and is ideal for space-limited, cost-sensitive embedded and consumer electronics such as portable media players (PMPs), industrial metering and monitoring, portable navigation devices (PNDs), handsets, digital cameras and hundreds of other handheld, power-sensitive products.
As part of Silicon Labs’ comprehensive, programmable timing portfolio, the Si512xx clocks are highly customizable devices. The Si512xx clock generators support up to three LVCMOS clock outputs from 3 to 200 MHz in a single device, providing developers with maximum flexibility while simplifying supply chain management. Each output has four levels of output strength setting, which can be configured individually to match the load and the trace length condition of the board. This is more than twice the configurability of the closest competing product.
The ultra-small Si512xx clocks typically use up to 80 percent less board space than competing clock generator ICs and provide cost-saving replacements for sub-200 MHz LVCMOS oscillators. By supporting multiple LVCMOS outputs, the single-chip Si512xx clock generators replace multiple surface-mounted crystals and oscillators with one economical device, further reducing board space and BOM cost.
In addition to unparalleled cost and space savings, these ultra-small clock generators also support green initiatives by reducing power consumption up to 60 percent compared to competing solutions. This 2x low-power advantage offers noteworthy benefits such as longer battery life in power-sensitive applications ranging from smart meters to handheld devices. The Si512xx clocks also provide output enable (OE) functionality to achieve even lower power modes in standby or sleep states.
The Si512xx clock generators provide customizable spread spectrum clocking technology to minimize electromagnetic interference (EMI). This frequency modulation technique enables system designers to reduce EMI by spreading clock energy over a wider frequency range, consequently reducing peak emissions at the fundamental frequency and every harmonic.
The Si512xx further reduces EMI and increases system margin for data integrity through an innovative approach to edge-rate slew customization. The Si512xx clock family’s highly flexible architecture can be factory-customized to support specific spread spectrum and edge-rate slewing profiles, percentages, modulation types and/or rates to meet customer specifications for output frequencies, control inputs and drive strength.
“No other small-footprint clock solution today offers the high level of integration, power efficiency and configurability of the Si512xx clock family,” said Mike Petrowski, GM of Silicon Labs’ timing products. “Like the rest of our timing device family, these clock generator ICs offer customers the industry’s shortest lead times for custom clocks to help streamline development cycles.”
Production quantities of Silicon Labs’ Si512xx clock generator products are available now in a choice of 1.4 mm x 1.2 mm 6-pin TDFN, 1.4 mm x 1.6 mm 8-pin TDFN and 8-pin TSSOP package options. Pricing in 50,000-unit quantities begins at $0.32 for 2-output clock generators. The Si51210-EVB evaluation board for 6-pin TDFN clocks, the Si51211-EVB for 8-pin TDFN clocks and the Si51219-EVB 8-pin TSSOP clocks are each priced at $50.
As part of Silicon Labs’ comprehensive, programmable timing portfolio, the Si512xx clocks are highly customizable devices. The Si512xx clock generators support up to three LVCMOS clock outputs from 3 to 200 MHz in a single device, providing developers with maximum flexibility while simplifying supply chain management. Each output has four levels of output strength setting, which can be configured individually to match the load and the trace length condition of the board. This is more than twice the configurability of the closest competing product.
The ultra-small Si512xx clocks typically use up to 80 percent less board space than competing clock generator ICs and provide cost-saving replacements for sub-200 MHz LVCMOS oscillators. By supporting multiple LVCMOS outputs, the single-chip Si512xx clock generators replace multiple surface-mounted crystals and oscillators with one economical device, further reducing board space and BOM cost.
In addition to unparalleled cost and space savings, these ultra-small clock generators also support green initiatives by reducing power consumption up to 60 percent compared to competing solutions. This 2x low-power advantage offers noteworthy benefits such as longer battery life in power-sensitive applications ranging from smart meters to handheld devices. The Si512xx clocks also provide output enable (OE) functionality to achieve even lower power modes in standby or sleep states.
The Si512xx clock generators provide customizable spread spectrum clocking technology to minimize electromagnetic interference (EMI). This frequency modulation technique enables system designers to reduce EMI by spreading clock energy over a wider frequency range, consequently reducing peak emissions at the fundamental frequency and every harmonic.
The Si512xx further reduces EMI and increases system margin for data integrity through an innovative approach to edge-rate slew customization. The Si512xx clock family’s highly flexible architecture can be factory-customized to support specific spread spectrum and edge-rate slewing profiles, percentages, modulation types and/or rates to meet customer specifications for output frequencies, control inputs and drive strength.
“No other small-footprint clock solution today offers the high level of integration, power efficiency and configurability of the Si512xx clock family,” said Mike Petrowski, GM of Silicon Labs’ timing products. “Like the rest of our timing device family, these clock generator ICs offer customers the industry’s shortest lead times for custom clocks to help streamline development cycles.”
Production quantities of Silicon Labs’ Si512xx clock generator products are available now in a choice of 1.4 mm x 1.2 mm 6-pin TDFN, 1.4 mm x 1.6 mm 8-pin TDFN and 8-pin TSSOP package options. Pricing in 50,000-unit quantities begins at $0.32 for 2-output clock generators. The Si51210-EVB evaluation board for 6-pin TDFN clocks, the Si51211-EVB for 8-pin TDFN clocks and the Si51219-EVB 8-pin TSSOP clocks are each priced at $50.
Monday, January 30, 2012
Lattice and Weikeng expand distribution agreement
HILLSBORO, USA: Lattice Semiconductor Corp. and Weikeng Industrial Co. Ltd have signed an expanded distribution agreement. Under the terms of the agreement, Weikeng Technology Pte Ltd. is authorized to sell Lattice's complete portfolio of innovative low power, low cost FPGA, PLD and programmable power management solutions across southeast Asia (Indonesia, Malaysia, Philippines, Singapore, Thailand and Vietnam), and India.
"The expanded Weikeng S.E.A. & India distributorship has marked an important milestone in bringing the Lattice-Weikeng relationship to new heights," said Sky Ng TT, MD of Weikeng Technology Pte Ltd. "We appreciate Lattice's confidence in us and look forward to serving a broader customer base with Lattice's compelling FPGA solutions."
"We are very pleased to expand our partnership with Weikeng, based on their strong position in the Asian market and their demand creation focused experience in supporting our devices," said Stacy Fender, Lattice corporate VP of Worldwide Sales. "Working with Weikeng Technology will significantly increase the sales coverage and support for our customers in these additional countries as well as provide Pan Asian support for those customers that have a presence in multiple locations."
"The expanded Weikeng S.E.A. & India distributorship has marked an important milestone in bringing the Lattice-Weikeng relationship to new heights," said Sky Ng TT, MD of Weikeng Technology Pte Ltd. "We appreciate Lattice's confidence in us and look forward to serving a broader customer base with Lattice's compelling FPGA solutions."
"We are very pleased to expand our partnership with Weikeng, based on their strong position in the Asian market and their demand creation focused experience in supporting our devices," said Stacy Fender, Lattice corporate VP of Worldwide Sales. "Working with Weikeng Technology will significantly increase the sales coverage and support for our customers in these additional countries as well as provide Pan Asian support for those customers that have a presence in multiple locations."
TI's advanced signal conditioners deliver industry's highest performance at lowest power
DALLAS, USA: Texas Instruments Inc. (TI) introduced 10 signal conditioners designed to drive high-speed interface standards such as 10G/40G/100G Ethernet, 10G-KR (802.3ap), InfiniBand, Fibre Channel and CPRI.
The new integrated circuits (ICs) join a comprehensive family of repeaters and retimers that combat signal impairments caused by insertion loss, jitter, reflections and crosstalk in high-speed enterprise servers, routers and switches. Manufactured using TI's high-performance BiCMOS SiGe process technology, these new signal conditioners deliver the industry's highest signal reach performance at less than 6-mW per gigabit.
"As transmission rates increase, signal integrity requirements become more stringent," said Linley Group senior analyst, Jag Bolaria. "Highly integrated ASIC and ASSP solutions with shrinking transistor geometries, lower voltage rails and lower output voltages further compound the problem, making systems more susceptible to random jitter and crosstalk interference. TI's new retimer and repeater products resolve these complex signal integrity impairments while consuming low power."
The new integrated circuits (ICs) join a comprehensive family of repeaters and retimers that combat signal impairments caused by insertion loss, jitter, reflections and crosstalk in high-speed enterprise servers, routers and switches. Manufactured using TI's high-performance BiCMOS SiGe process technology, these new signal conditioners deliver the industry's highest signal reach performance at less than 6-mW per gigabit.
"As transmission rates increase, signal integrity requirements become more stringent," said Linley Group senior analyst, Jag Bolaria. "Highly integrated ASIC and ASSP solutions with shrinking transistor geometries, lower voltage rails and lower output voltages further compound the problem, making systems more susceptible to random jitter and crosstalk interference. TI's new retimer and repeater products resolve these complex signal integrity impairments while consuming low power."
Altium collaborates with Altera to release online component resources and software support
CARLSBAD, USA: Altium, developer of next-generation electronics design software and services, announced new devices and updates to the board-level components from Altera's Stratix IV FPGA and MAX V CPLD device families available in its online content delivery ecosystem, AltiumLive.
The release coincides with the inclusion of Altera Stratix IV FPGA and MAX V CPLD device support in the latest update for Altium Designer 10, Altium's unified electronics design system.
Developed in collaboration with Altera, the updated collection of FPGA and CPLD components add to the extensive range of Altera design content already available through AltiumLive. The new components are available through the AltiumLive portal from within Altium Designer, providing designers with access to current, high quality board-level components during the design process.
Altium Designer includes comprehensive software support for the newly updated Altera devices, allowing their full integration into the programmable device design part of the electronics design flow. This provides the unique design conditions for working with a specific programmable device, such as pin configurations and I/O type, live communication protocols, synthesis and PCB pin swapping data, making the Altera devices ready for easy, rapid deployment in Altium Designer projects.
The collaborative relationship between Altera and Altium is another significant step in the expansion of Altium's partnership program, which aims to forge collaborative relationships with a broad group of electronic component manufacturers and distributors.
The strategic partnerships ultimately allow Altium to deliver quality online content and services directly to Altium Designer users. Along with device manufacturers such as Altera, Altium has also established relationships with parts suppliers and vendors such as Farnell, Digi-Key and Newark. This allows board-level components to include real-time supply-chain information, such as vendor choice, pricing and availability.
"Collaboration between Altium and parts manufacturers helps us produce high-integrity design IP for our customers," said Rowland Washington, content development manager for Altium. "We are pleased to be working with Altera to develop an ever-increasing range of third party libraries, templates, reference designs and other ready-to-use design content."
This latest update to the Altera board-level component content available through AltiumLive includes a full update of the Stratix IV high-performance FPGA family and the addition of the MAX V low power CPLD range – Altium Designer 10 now provides design software support for these devices. The update adds to the already substantial collection of Altera programmable devices available from AltiumLive's board-level component vault, which includes Altera's broad portfolio of high-end, low-cost and mid-range FPGA families and CPLDs, including Stratix FPGAs, Cyclone FPGAs, Arria FPGAs, and MAX CPLDs.
"Working with Altium to deliver online design content will bring high quality Altera component models directly to the desktop of designers using Altium Designer," said Patrick Dorsey, senior director of component product marketing at Altera Corporation. "This makes it faster and easier for customers to use Altera devices in their designs using up-to-date, quality design resources."
The new and existing Altera components are available online through AltiumLive's board-level component vault, one of Altium's managed component repositories of ready-to-use design elements accessible through the AltiumLive portal. Designers can directly access the components and linked supplier information from within Altium
Designer when using a subscription-enabled license, or by browsing to the AltiumLive Content Store via the web. Designers installing the latest update for Altium Designer 10 will have access to complete design-time software support for the new Altera devices.
The release coincides with the inclusion of Altera Stratix IV FPGA and MAX V CPLD device support in the latest update for Altium Designer 10, Altium's unified electronics design system.
Developed in collaboration with Altera, the updated collection of FPGA and CPLD components add to the extensive range of Altera design content already available through AltiumLive. The new components are available through the AltiumLive portal from within Altium Designer, providing designers with access to current, high quality board-level components during the design process.
Altium Designer includes comprehensive software support for the newly updated Altera devices, allowing their full integration into the programmable device design part of the electronics design flow. This provides the unique design conditions for working with a specific programmable device, such as pin configurations and I/O type, live communication protocols, synthesis and PCB pin swapping data, making the Altera devices ready for easy, rapid deployment in Altium Designer projects.
The collaborative relationship between Altera and Altium is another significant step in the expansion of Altium's partnership program, which aims to forge collaborative relationships with a broad group of electronic component manufacturers and distributors.
The strategic partnerships ultimately allow Altium to deliver quality online content and services directly to Altium Designer users. Along with device manufacturers such as Altera, Altium has also established relationships with parts suppliers and vendors such as Farnell, Digi-Key and Newark. This allows board-level components to include real-time supply-chain information, such as vendor choice, pricing and availability.
"Collaboration between Altium and parts manufacturers helps us produce high-integrity design IP for our customers," said Rowland Washington, content development manager for Altium. "We are pleased to be working with Altera to develop an ever-increasing range of third party libraries, templates, reference designs and other ready-to-use design content."
This latest update to the Altera board-level component content available through AltiumLive includes a full update of the Stratix IV high-performance FPGA family and the addition of the MAX V low power CPLD range – Altium Designer 10 now provides design software support for these devices. The update adds to the already substantial collection of Altera programmable devices available from AltiumLive's board-level component vault, which includes Altera's broad portfolio of high-end, low-cost and mid-range FPGA families and CPLDs, including Stratix FPGAs, Cyclone FPGAs, Arria FPGAs, and MAX CPLDs.
"Working with Altium to deliver online design content will bring high quality Altera component models directly to the desktop of designers using Altium Designer," said Patrick Dorsey, senior director of component product marketing at Altera Corporation. "This makes it faster and easier for customers to use Altera devices in their designs using up-to-date, quality design resources."
The new and existing Altera components are available online through AltiumLive's board-level component vault, one of Altium's managed component repositories of ready-to-use design elements accessible through the AltiumLive portal. Designers can directly access the components and linked supplier information from within Altium
Designer when using a subscription-enabled license, or by browsing to the AltiumLive Content Store via the web. Designers installing the latest update for Altium Designer 10 will have access to complete design-time software support for the new Altera devices.
Microchip announces 25 percent performance increase to dsPIC DSCs for digital-power apps
CHANDLER, USA: Microchip Technology Inc. announced a 25 percent performance increase on its dsPIC33F “GS” series of Digital Signal Controllers (DSCs) for Switch Mode Power Supplies (SMPSs).
Now featuring 50 MIPS performance, the dsPIC33F “GS” series of DSCs include on-chip peripherals for digital-power applications, such as an Analog-to-Digital Converter (ADC), Pulse Width Modulation (PWM) peripheral and analog comparators. The dsPIC33F “GS” family supports applications such as Induction Cooking, Uninterrupted Power Supplies (UPSs), Inverters, Intelligent Battery Chargers, Power Factor Correction, HID Lighting, Fluorescent Lighting, LED Lighting, and AC-to-DC, as well as DC-to-DC Power-Conversion applications.
The dsPIC33F “GS” DSCs are available in 28- to 100-pin packages, with 16 – 64K of Flash. The on-chip ADC operates at up to 4 Msps, and the PWM peripherals provide up to 1 nanosecond resolution, with modes supporting all power-conversion topologies. Additionally, the DSCs feature up to four on-chip analog comparators with integrated on-chip Digital-to-Analog Converters, enabling designers to set trip levels dynamically. The analog comparators can be used to directly control the PWM functions.
“With 50 MIPS of performance, our customers can now aim to achieve better efficiencies in their power-supply applications,” said Sumit Mitra, VP of Microchip’s High-Performance Microcontroller Division. “These new devices feature industry-leading on-chip peripherals specifically designed for digital power supplies. Customers can fully control their products using a single ‘GS’ dsPIC DSC at a lower system cost, with more features.”
Now featuring 50 MIPS performance, the dsPIC33F “GS” series of DSCs include on-chip peripherals for digital-power applications, such as an Analog-to-Digital Converter (ADC), Pulse Width Modulation (PWM) peripheral and analog comparators. The dsPIC33F “GS” family supports applications such as Induction Cooking, Uninterrupted Power Supplies (UPSs), Inverters, Intelligent Battery Chargers, Power Factor Correction, HID Lighting, Fluorescent Lighting, LED Lighting, and AC-to-DC, as well as DC-to-DC Power-Conversion applications.
The dsPIC33F “GS” DSCs are available in 28- to 100-pin packages, with 16 – 64K of Flash. The on-chip ADC operates at up to 4 Msps, and the PWM peripherals provide up to 1 nanosecond resolution, with modes supporting all power-conversion topologies. Additionally, the DSCs feature up to four on-chip analog comparators with integrated on-chip Digital-to-Analog Converters, enabling designers to set trip levels dynamically. The analog comparators can be used to directly control the PWM functions.
“With 50 MIPS of performance, our customers can now aim to achieve better efficiencies in their power-supply applications,” said Sumit Mitra, VP of Microchip’s High-Performance Microcontroller Division. “These new devices feature industry-leading on-chip peripherals specifically designed for digital power supplies. Customers can fully control their products using a single ‘GS’ dsPIC DSC at a lower system cost, with more features.”
RFaxis celebrates four-year anniversary by shipping four-millionth RFeIC
IRVINE, USA: RFaxis, a fabless semiconductor company focused on innovative, next-generation Radio Frequency (RF) solutions for the wireless connectivity and cellular mobility markets, celebrated two milestones: shipping four million units of its patented single-chip/single-die RF Front-end ICs (RFeIC) and its four-year anniversary.
“RFaxis was incorporated in January 2008, amidst one of the most severe global business downturns in history. At a time when almost every company in the world was either downsizing or going out of business, we started RFaxis. There were major economic doubts whether any startup could succeed, much less survive. Many experts in the RF field did not believe RFaxis could ever deliver a fully integrated single-chip/single-die RF Frond-End. The odds were stacked against us,” said Mike Neshat, chairman and CEO of RFaxis.
“Time has been our best judge, and our innovative corporate culture has silenced the critics. The shipment of our four-millionth RFeIC, which is being used in many products and serving several markets - from Wi-Fi to Smart Meters to Home Automation - is the best testimony of the tremendous value that RFaxis brings to the wireless ecosystem.”
For its pioneering work in bringing fresh ideas and major innovations to the global wireless and RF community, RFaxis has received several major awards since its inception, including the prestigious 2010 EE Times ACE Award for “Start-up of the Year,” EE Times “Silicon 60,” the 2011 Red Herring Top 100 North America Award, and the TechAmerica 18th Annual OC High-Tech Innovation Award.
“With Wi-Fi enabled devices projected to reach 2.6 billion annual shipments by 2016, and Internet of Things with up to 50 billion connections gradually becoming a natural part of consumer lifestyles and business operations, we firmly believe RFaxis’ pure CMOS RFeIC solutions are on solid path to becoming the next mainstream in RF, as we initially envisioned when started the company. In fact, based on our existing design wins and customers’ demand, we will be shipping in excess of 50 million RFeICs in 2012. Our goal is to beat this number as we win more sockets,” concluded Neshat.
“RFaxis was incorporated in January 2008, amidst one of the most severe global business downturns in history. At a time when almost every company in the world was either downsizing or going out of business, we started RFaxis. There were major economic doubts whether any startup could succeed, much less survive. Many experts in the RF field did not believe RFaxis could ever deliver a fully integrated single-chip/single-die RF Frond-End. The odds were stacked against us,” said Mike Neshat, chairman and CEO of RFaxis.
“Time has been our best judge, and our innovative corporate culture has silenced the critics. The shipment of our four-millionth RFeIC, which is being used in many products and serving several markets - from Wi-Fi to Smart Meters to Home Automation - is the best testimony of the tremendous value that RFaxis brings to the wireless ecosystem.”
For its pioneering work in bringing fresh ideas and major innovations to the global wireless and RF community, RFaxis has received several major awards since its inception, including the prestigious 2010 EE Times ACE Award for “Start-up of the Year,” EE Times “Silicon 60,” the 2011 Red Herring Top 100 North America Award, and the TechAmerica 18th Annual OC High-Tech Innovation Award.
“With Wi-Fi enabled devices projected to reach 2.6 billion annual shipments by 2016, and Internet of Things with up to 50 billion connections gradually becoming a natural part of consumer lifestyles and business operations, we firmly believe RFaxis’ pure CMOS RFeIC solutions are on solid path to becoming the next mainstream in RF, as we initially envisioned when started the company. In fact, based on our existing design wins and customers’ demand, we will be shipping in excess of 50 million RFeICs in 2012. Our goal is to beat this number as we win more sockets,” concluded Neshat.
Mentor Graphics announces major new function in HyperLynx release 8.2
DesignCon 2012, SANTA CLARA, USA: Mentor Graphics Corp. announced the release of version 8.2 of the HyperLynx suite of analysis tools offering significant new functionality for optimizing printed circuit board (PCB) designs, including 3D full-wave field solving, and integrated thermal/power co-simulation analysis capabilities. Analysis of today’s multi-GHz SERDES channel interconnects—such as PCIe-Gen 3—requires specialized 3D modeling for accurate signal integrity analysis.
Another major feature is the integration of the HyperLynx Thermal analysis with the HyperLynx PI (power integrity) products to calculate the affects of heat generated by areas of high current density in complex power distribution networks (PDNs) on the PCB. These major enhancements enable HyperLynx users to reliably utilize the industry’s most advanced high-speed IC and PCB technologies while developing more competitive products and hitting tight market windows.
For digital serial interconnects operating in data rate ranges of 5 to 28Gbps, it is important to include the 3D effects of certain PCB structures, such as vias, in the signal integrity analysis. However, analyzing the complete interconnect using full-wave 3D field analysis would not be practical, as the computing times would be excessive. Using a new feature in the HyperLynx 8.2 product, analysis is performed with 3D full-wave models for structures such as vias, and with 2D/2.5D solutions for constructs such as traces. The result is fast and accurate full interconnect analysis.
“We’ve used the new HyperLynx LineSim interface 3D EM solver to analyze our vias for very high-speed interconnects,” said Yanfeng Yu, principal engineer, ZTE Corp. “This feature is one of the must-have features for serial channel design. It’s easy to use and the performance is very good.”
Another effect of today’s more advanced, high-performance designs is the necessity for multiple and complex power distribution networks due to the increasing number of supply voltages. This complexity can result in neck-down areas of copper on the PCB and high current densities which can then lead to excessive copper heating and, in severe cases, copper failure.
The HyperLynx PI product now includes co-simulation between power integrity DC and thermal analysis to reflect the combination of heating of the PDNs and heat dissipation from the components, and the increased copper resistivity due to this heating. These integrated products now alert the designer to possible product failures due to excessive heat, as well as possible signal/power integrity performance issues.
“This merging of signal/power integrity and thermal analysis is yet another example of how once isolated design disciplines are affecting each other,” said Dave Kohlmeier, director of analysis products, Systems Design Division, Mentor Graphics. “Mentor’s strategy of creating an integrated suite of analysis tools that allow collaboration among the many disciplines involved in the product development process is enabling our customers to deliver more advanced and competitive products to market faster and with higher quality.”
Another major feature is the integration of the HyperLynx Thermal analysis with the HyperLynx PI (power integrity) products to calculate the affects of heat generated by areas of high current density in complex power distribution networks (PDNs) on the PCB. These major enhancements enable HyperLynx users to reliably utilize the industry’s most advanced high-speed IC and PCB technologies while developing more competitive products and hitting tight market windows.
For digital serial interconnects operating in data rate ranges of 5 to 28Gbps, it is important to include the 3D effects of certain PCB structures, such as vias, in the signal integrity analysis. However, analyzing the complete interconnect using full-wave 3D field analysis would not be practical, as the computing times would be excessive. Using a new feature in the HyperLynx 8.2 product, analysis is performed with 3D full-wave models for structures such as vias, and with 2D/2.5D solutions for constructs such as traces. The result is fast and accurate full interconnect analysis.
“We’ve used the new HyperLynx LineSim interface 3D EM solver to analyze our vias for very high-speed interconnects,” said Yanfeng Yu, principal engineer, ZTE Corp. “This feature is one of the must-have features for serial channel design. It’s easy to use and the performance is very good.”
Another effect of today’s more advanced, high-performance designs is the necessity for multiple and complex power distribution networks due to the increasing number of supply voltages. This complexity can result in neck-down areas of copper on the PCB and high current densities which can then lead to excessive copper heating and, in severe cases, copper failure.
The HyperLynx PI product now includes co-simulation between power integrity DC and thermal analysis to reflect the combination of heating of the PDNs and heat dissipation from the components, and the increased copper resistivity due to this heating. These integrated products now alert the designer to possible product failures due to excessive heat, as well as possible signal/power integrity performance issues.
“This merging of signal/power integrity and thermal analysis is yet another example of how once isolated design disciplines are affecting each other,” said Dave Kohlmeier, director of analysis products, Systems Design Division, Mentor Graphics. “Mentor’s strategy of creating an integrated suite of analysis tools that allow collaboration among the many disciplines involved in the product development process is enabling our customers to deliver more advanced and competitive products to market faster and with higher quality.”
Avago demos industry’s first 28-nm 25-Gbps long reach-compliant ASIC SerDes for networking equipment
DesignCon 2012, SAN JOSE, USA & SINGAPORE: Avago Technologies announced that its 25-Gbps Serializer/Deserializer (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). Achieving CEI-25G-LR compliance eases design of data networking applications and aligns with the push for 100G Ethernet Infrastructure to extend cloud computing, multimedia and virtualization capabilities.
Avago also announced it will demonstrate its 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition in the Santa Clara Convention Center in Santa Clara, California from Jan. 31 to Feb. 1. The embedded SerDes cores are often integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The demonstrations, which show the Avago 25G SerDes running on over 30-inch PC board traces, will take place in the TE Connectivity booth (#411) and in the Amphenol TCS booth (#501).
“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, VP and GM of ASIC Products Division at Avago. “As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers.”
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture, and Avago has integrated over 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
Avago has an established history of delivering on-time, reliable, high-performance ASICs. Three decades of design experience, state-of-the art hierarchical design methodology, and an IP portfolio covering multiple standards form the company’s foundation for supplying complex ASICs to the wired communications market. The broad Avago SerDes portfolio supports a wide range of standards such as PCI Express, Fibre Channel, XAUI, CEI, 10GBASE-KR and SFI, providing the flexibility to address optical, copper and backplane applications.
Avago also announced it will demonstrate its 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition in the Santa Clara Convention Center in Santa Clara, California from Jan. 31 to Feb. 1. The embedded SerDes cores are often integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The demonstrations, which show the Avago 25G SerDes running on over 30-inch PC board traces, will take place in the TE Connectivity booth (#411) and in the Amphenol TCS booth (#501).
“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, VP and GM of ASIC Products Division at Avago. “As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers.”
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture, and Avago has integrated over 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
Avago has an established history of delivering on-time, reliable, high-performance ASICs. Three decades of design experience, state-of-the art hierarchical design methodology, and an IP portfolio covering multiple standards form the company’s foundation for supplying complex ASICs to the wired communications market. The broad Avago SerDes portfolio supports a wide range of standards such as PCI Express, Fibre Channel, XAUI, CEI, 10GBASE-KR and SFI, providing the flexibility to address optical, copper and backplane applications.
ISA Vision Summit 2012 to be held in Bangalore
BANGALORE, INDIA: India Semiconductor Association (ISA), the apex trade body representing the Indian semiconductor and electronics industry, announced that the seventh edition of the flagship annual conference, ISA Vision Summit will be held in Bangalore on Feb. 6-7, 2012 at Hotel Taj West End, Bangalore.
The chief guest would be Kapil Sibal, Hon'ble Minister for HRD, Communications & IT, Government of India. The inaugural address would be given by Sachin Pilot, Hon'ble Minister of State for Communications & IT, Government of India. Other distinguished guests include R Chandrashekar, Secretary Dept. of IT and Dept. of Telecom, Government of India and MN Vidyashankar, Principal Secretary, e-Governance Dept. & Principal Secretary (I/c.), IT, BT and S&T Dept., Government of Karnataka.
The ISA Vision Summit is a high-powered conclave with participation of global and Indian leaders from the Electronic Systems Design and Manufacturing (ESDM) industry. The two day event would have more than 500 industry and government leaders, various international business delegations, and over 25 speakers. There would be focused sessions on sector opportunities, market trends, policy directives along with exclusive sessions with innovators and entrepreneurs. During the Summit, winners from ISA’s Technovation Awards 2011 would also be present.
Dr. Pradip K. Dutta, chairman ISA, and corporate VP and MD, Synopsys India, said: “Semiconductors and electronics are at the heart of technology driven products that will drive the $400 billion Indian electronics market by 2020. ISA is committed to working with all the stake-holders from industry, academia and government to enable the eco-system that will convert this opportunity into reality.”
PVG Menon, president of ISA, said: "The Indian electronics market is poised on the verge of spectacular growth. India will grow to become a $400 billion electronics market by 2020. Several factors have to come to play to make that happen, and ISA Vision Summit will examine those issues. We have an exciting line-up of speakers and we’re sure that the delegates will have very useful take-away’s from this power-packed Summit.”
The theme of the conference for this year is “Growth drivers for emerging markets: Semiconductors and Electronic Systems.”
Dr. Aart de Geus, chairman of the Board and CEO, Synopsys, will deliver a keynote address on the changing design eco-system in India. Dr. Walden C. Rhines, CEO and chairman of the Board, Mentor Graphics Inc., will deliver a keynote address on how to build fabless semiconductor companies in India. Pradeep N. Dhoot, group president of Videocon Industries will deliver a keynote address on building globally competitive electronics manufacturing out of India. Ajai Chowdhury, founder and chairman of HCL Infosystems, will deliver a keynote address examining how the future of electronics manufacturing lies in India.
In addition to this, several global leaders from the industry, as well as senior government leaders from India will address delegates about various aspects of the ESDM sector.
ISA Vision Summit 2012 also introduces for the first time a B2B deal-making session, wherein an attempt is being made to connect buyers and sellers. A unique feature is the special focus on SMEs and in getting them connected with international and domestic buyers.
The chief guest would be Kapil Sibal, Hon'ble Minister for HRD, Communications & IT, Government of India. The inaugural address would be given by Sachin Pilot, Hon'ble Minister of State for Communications & IT, Government of India. Other distinguished guests include R Chandrashekar, Secretary Dept. of IT and Dept. of Telecom, Government of India and MN Vidyashankar, Principal Secretary, e-Governance Dept. & Principal Secretary (I/c.), IT, BT and S&T Dept., Government of Karnataka.
The ISA Vision Summit is a high-powered conclave with participation of global and Indian leaders from the Electronic Systems Design and Manufacturing (ESDM) industry. The two day event would have more than 500 industry and government leaders, various international business delegations, and over 25 speakers. There would be focused sessions on sector opportunities, market trends, policy directives along with exclusive sessions with innovators and entrepreneurs. During the Summit, winners from ISA’s Technovation Awards 2011 would also be present.
Dr. Pradip K. Dutta, chairman ISA, and corporate VP and MD, Synopsys India, said: “Semiconductors and electronics are at the heart of technology driven products that will drive the $400 billion Indian electronics market by 2020. ISA is committed to working with all the stake-holders from industry, academia and government to enable the eco-system that will convert this opportunity into reality.”
PVG Menon, president of ISA, said: "The Indian electronics market is poised on the verge of spectacular growth. India will grow to become a $400 billion electronics market by 2020. Several factors have to come to play to make that happen, and ISA Vision Summit will examine those issues. We have an exciting line-up of speakers and we’re sure that the delegates will have very useful take-away’s from this power-packed Summit.”
The theme of the conference for this year is “Growth drivers for emerging markets: Semiconductors and Electronic Systems.”
Dr. Aart de Geus, chairman of the Board and CEO, Synopsys, will deliver a keynote address on the changing design eco-system in India. Dr. Walden C. Rhines, CEO and chairman of the Board, Mentor Graphics Inc., will deliver a keynote address on how to build fabless semiconductor companies in India. Pradeep N. Dhoot, group president of Videocon Industries will deliver a keynote address on building globally competitive electronics manufacturing out of India. Ajai Chowdhury, founder and chairman of HCL Infosystems, will deliver a keynote address examining how the future of electronics manufacturing lies in India.
In addition to this, several global leaders from the industry, as well as senior government leaders from India will address delegates about various aspects of the ESDM sector.
ISA Vision Summit 2012 also introduces for the first time a B2B deal-making session, wherein an attempt is being made to connect buyers and sellers. A unique feature is the special focus on SMEs and in getting them connected with international and domestic buyers.
NetLogic announces industry’s first open–source Xen Hypervisor for multi-core MIPS64 processors
SANTA CLARA, USA: NetLogic Microsystems Inc. announced the industry’s first open–source Xen hypervisor for high-performance multi-core MIPS64 processors. The new XEN hypervisor from NetLogic Microsystems enables highly efficient virtualization for next-generation communications, networking and server platforms using the industry’s best-in-class XLP and XLP II multi-core, multi-threaded processors.
Service providers, data centers and enterprises are increasingly embracing virtualization to increase hardware processing utilization and efficiency, unify networking and server farms, and reduce complexity and total cost of ownership. The Xen hypervisor is a fast and secure infrastructure virtualization solution that enables multiple instances of the same or different operating systems on a single processor.
Each operating system will not only run completely independently, but also securely so that the software running on one operating system is protected from that on another operating system. Multiple applications, therefore, can run on a single processor, but operate completely independently from each other. This allows developers the opportunity to create compact, multi-function systems solutions that take full advantage of multi-core processors while minimizing power consumption.
For example, a base station can be designed to provide both 3G and LTE services with a single processor, ultimately reducing the cost and complexity of the hardware, while enhancing the flexibility and capability of the system solution.
NetLogic Microsystems’ XLP and XLP II multi-core, multi-threaded processors are the industry’s most advanced, highest performance communications processors that feature an innovative quad-issue, quad-threaded and superscalar architecture with out-of-order execution capabilities. This uniquely superior architecture makes the industry-leading XLP and XLP II processor families ideally suited for the virtualization of multiple applications and multiple operating systems on each of the high-performance cores.
The flagship XLP processor family in 40nm operates at up to 2GHz and delivers cache-coherent scalability of up to 128 NXCPUs, while the next-generation XLP II processor family is designed for up to 2.5GHz and scalability up to 640 NXCPUs in the state-of-the-art 28nm process.
The Xen hypervisor is a thin software layer that resides between the operating system and the processor, thus providing an abstraction layer that allows each processor to run as multiple virtualized processors. As a unique open-source technology, the Xen hypervisor is developed collaboratively by a broad community comprising leading system original equipment manufacturers (OEMs), software and application providers, and semiconductor vendors.
The Xen hypervisor from NetLogic Microsystems is freely accessible through the Xen open-source community. This will enable customers and third-party developers to easily incorporate and extend their systems solutions using the best-in-class XLP and XLP II multi-core processors.
Service providers, data centers and enterprises are increasingly embracing virtualization to increase hardware processing utilization and efficiency, unify networking and server farms, and reduce complexity and total cost of ownership. The Xen hypervisor is a fast and secure infrastructure virtualization solution that enables multiple instances of the same or different operating systems on a single processor.
Each operating system will not only run completely independently, but also securely so that the software running on one operating system is protected from that on another operating system. Multiple applications, therefore, can run on a single processor, but operate completely independently from each other. This allows developers the opportunity to create compact, multi-function systems solutions that take full advantage of multi-core processors while minimizing power consumption.
For example, a base station can be designed to provide both 3G and LTE services with a single processor, ultimately reducing the cost and complexity of the hardware, while enhancing the flexibility and capability of the system solution.
NetLogic Microsystems’ XLP and XLP II multi-core, multi-threaded processors are the industry’s most advanced, highest performance communications processors that feature an innovative quad-issue, quad-threaded and superscalar architecture with out-of-order execution capabilities. This uniquely superior architecture makes the industry-leading XLP and XLP II processor families ideally suited for the virtualization of multiple applications and multiple operating systems on each of the high-performance cores.
The flagship XLP processor family in 40nm operates at up to 2GHz and delivers cache-coherent scalability of up to 128 NXCPUs, while the next-generation XLP II processor family is designed for up to 2.5GHz and scalability up to 640 NXCPUs in the state-of-the-art 28nm process.
The Xen hypervisor is a thin software layer that resides between the operating system and the processor, thus providing an abstraction layer that allows each processor to run as multiple virtualized processors. As a unique open-source technology, the Xen hypervisor is developed collaboratively by a broad community comprising leading system original equipment manufacturers (OEMs), software and application providers, and semiconductor vendors.
The Xen hypervisor from NetLogic Microsystems is freely accessible through the Xen open-source community. This will enable customers and third-party developers to easily incorporate and extend their systems solutions using the best-in-class XLP and XLP II multi-core processors.
Microsemi intros energy-efficient PoE (EEPoE) midspans
ALISO VIEJO, USA & LONDON, UK: Microsemi Corp. announced its new high-efficiency Power-over-Ethernet (PoE) midspans at the Cisco Live London show. The new PoE devices reduce energy consumption on network cables by as much as 50 percent compared to alternative midspans and PoE network switches.
The Microsemi PowerDsine PD-5524G EEPoE midspan complies with IEEE802.3at 2009 standards for delivering up to 30 watts (W) of power to network devices including IP cameras, access control systems and thin clients, over the same standard CAT5 cabling as data. Microsemi is demonstrating its new midspans at Cisco Live London in booth #E87 Jan. 30-Feb. 3.
"Microsemi has achieved yet another major milestone in the energy-saving capabilities of PoE technology," said Amir Asvadi, VP and GM of the Analog Mixed Signal Group at Microsemi. "Our PD-5524G EEPoE midspan extends the industry-leading efficiency of our PowerDsine family by using a smaller internal power supply that can later be augmented with external supplies to increase per-port capacity as power-hungry devices are added to the network. Customers can optimize their power infrastructure for the highest possible efficiency today, and increase power delivery as demand grows."
Microsemi's 24-port PD-5524G midspan cuts the Ethernet cable energy dissipation by 50 percent, which equates to 240 kilowatt hours (KWh) in annual energy savings assuming continuous operation across 12 ports at full power. With electricity costs averaging approximately $0.15/KWh, this reduction in energy usage can yield up to $600 in savings over a 16-year midspan product life cycle.
Additional energy savings are possible using the PD-5524G midspan's PowerView Pro secure remote power management features, which enable network administrators to monitor and control power devices (PDs) and their power consumption after hours and on holidays and weekends. Use of the PowerView Pro scheduler to restrict power delivery to five 12-hour weekday cycles can yield additional savings of $300 per year, or $4,800 over the midspan life cycle.
The PD-5524G midspan uses technology pioneered in the company's PD-9500G family to significantly reduce power dissipation and energy consumption by delivering power over all four pairs of CAT5 cabling. The PD-5524G midspan is also the first to leverage a distributed power architecture, which enables smaller internal power supplies to be used for real-time requirements and then augmented incrementally, as needed, with Microsemi PowerDsine RPS 450 units or other external switching power supplies.
The midspan supports 10/100/1000BaseT data rates and complies with IEEE802.3at standards to more easily support high-power devices such as PTZ cameras, WLAN access points and thin clients.
"Our EEPoE midspans reduce power losses up to 2.25W per link as compared to any alternative PoE solution currently available in the market, including PoE switches and PoE midspans," said Sani Ronen, director of marketing for PoE systems at Microsemi. "The ability to add external power supplies not only delivers power scalability but also provides the means to back-up priority ports in the event of a primary supply failure. Multiple PD-5524G midspans also may be configured for mutual midspan-to-midspan backup."
Microsemi's PD-5524G EEPoE midspan reduces power dissipation for any standards-compliant PD that is attached to the network, including new PDs and any of the more than 100 million that have already been deployed. The company's patented EEPoE technology is also used in its PD70x0x ICs, which implement four-pair powering and other techniques for minimizing power losses, dissipation and consumption to enable the development of smaller and more energy-efficient PDs.
Microsemi's EEPoE products are part of a broad range of both two- and four-pair, standard- and high-power PoE solutions, including PSE ICs, splitters, and both managed and unmanaged midspan products in single- to 24-port configurations, with secure remote management capabilities and both IPv4 and IPv6 addressing support.
The Microsemi PowerDsine PD-5524G EEPoE midspan complies with IEEE802.3at 2009 standards for delivering up to 30 watts (W) of power to network devices including IP cameras, access control systems and thin clients, over the same standard CAT5 cabling as data. Microsemi is demonstrating its new midspans at Cisco Live London in booth #E87 Jan. 30-Feb. 3.
"Microsemi has achieved yet another major milestone in the energy-saving capabilities of PoE technology," said Amir Asvadi, VP and GM of the Analog Mixed Signal Group at Microsemi. "Our PD-5524G EEPoE midspan extends the industry-leading efficiency of our PowerDsine family by using a smaller internal power supply that can later be augmented with external supplies to increase per-port capacity as power-hungry devices are added to the network. Customers can optimize their power infrastructure for the highest possible efficiency today, and increase power delivery as demand grows."
Microsemi's 24-port PD-5524G midspan cuts the Ethernet cable energy dissipation by 50 percent, which equates to 240 kilowatt hours (KWh) in annual energy savings assuming continuous operation across 12 ports at full power. With electricity costs averaging approximately $0.15/KWh, this reduction in energy usage can yield up to $600 in savings over a 16-year midspan product life cycle.
Additional energy savings are possible using the PD-5524G midspan's PowerView Pro secure remote power management features, which enable network administrators to monitor and control power devices (PDs) and their power consumption after hours and on holidays and weekends. Use of the PowerView Pro scheduler to restrict power delivery to five 12-hour weekday cycles can yield additional savings of $300 per year, or $4,800 over the midspan life cycle.
The PD-5524G midspan uses technology pioneered in the company's PD-9500G family to significantly reduce power dissipation and energy consumption by delivering power over all four pairs of CAT5 cabling. The PD-5524G midspan is also the first to leverage a distributed power architecture, which enables smaller internal power supplies to be used for real-time requirements and then augmented incrementally, as needed, with Microsemi PowerDsine RPS 450 units or other external switching power supplies.
The midspan supports 10/100/1000BaseT data rates and complies with IEEE802.3at standards to more easily support high-power devices such as PTZ cameras, WLAN access points and thin clients.
"Our EEPoE midspans reduce power losses up to 2.25W per link as compared to any alternative PoE solution currently available in the market, including PoE switches and PoE midspans," said Sani Ronen, director of marketing for PoE systems at Microsemi. "The ability to add external power supplies not only delivers power scalability but also provides the means to back-up priority ports in the event of a primary supply failure. Multiple PD-5524G midspans also may be configured for mutual midspan-to-midspan backup."
Microsemi's PD-5524G EEPoE midspan reduces power dissipation for any standards-compliant PD that is attached to the network, including new PDs and any of the more than 100 million that have already been deployed. The company's patented EEPoE technology is also used in its PD70x0x ICs, which implement four-pair powering and other techniques for minimizing power losses, dissipation and consumption to enable the development of smaller and more energy-efficient PDs.
Microsemi's EEPoE products are part of a broad range of both two- and four-pair, standard- and high-power PoE solutions, including PSE ICs, splitters, and both managed and unmanaged midspan products in single- to 24-port configurations, with secure remote management capabilities and both IPv4 and IPv6 addressing support.
MagnaChip and GMT announce volume ramp of GMT's power management IC for LCD TV
SEOUL, SOUTH KOREA & CUPERTINO, USA: MagnaChip Semiconductor Corp., a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, and GMT (Global Mixed-mode Technology), a leading fabless provider of power solutions for mobile phone and PC applications, announced that MagnaChip has ramped to mass production GMT's power management IC (PMIC) products utilizing 0.35um BCD (Bipolar CMOS-DMOS) process technology.
MagnaChip and GMT have been engaged in the development of PMIC and LED Driver IC products using 0.35um 65V BCD process technology at MagnaChip's manufacturing facility located in Cheongju, South Korea. MagnaChip has successfully completed the final qualification of PMIC products which have ramped to high-volume production, while the LED driver IC products are currently under development.
The PMIC manages multiple power levels for LCD TV and monitor applications. GMT's PMIC incorporates a high-performance linear regulator, low-power charge-pump regulators, a high current operational amplifier and a logic-controlled gate-on pulse modulator to control the positive charge-pump output sequence and waveform. MagnaChip is uniquely positioned as a foundry provider to be able to offer the deep trench isolation technology for PMIC applications.
In addition to the PMIC, GMT's LED Driver IC has the ability to drive up to 12 parallel strings of LEDs at a maximum of 120mA of current. It also provides a precision current balance function for each LED string. Additionally, the LED string voltages can be up to a maximum of 65V. This makes it very suitable to be used in main stream (40 inch ~ 55 inch) LED TV back light applications.
Namkyu Park, VP of MagnaChip's Foundry Marketing, commented: "We are very pleased to announce MagnaChip's production ramp of GMT's PMIC products using our 0.35um BCD process technology. The continued introduction of these robust PMIC solutions is a direct result of the combined expertise of MagnaChip's manufacturing services and GMT's design engineering. We will continue to develop highly differentiated and cost-effective BCD technology solutions to meet the increasing application specific needs of our foundry customers."
MagnaChip and GMT have been engaged in the development of PMIC and LED Driver IC products using 0.35um 65V BCD process technology at MagnaChip's manufacturing facility located in Cheongju, South Korea. MagnaChip has successfully completed the final qualification of PMIC products which have ramped to high-volume production, while the LED driver IC products are currently under development.
The PMIC manages multiple power levels for LCD TV and monitor applications. GMT's PMIC incorporates a high-performance linear regulator, low-power charge-pump regulators, a high current operational amplifier and a logic-controlled gate-on pulse modulator to control the positive charge-pump output sequence and waveform. MagnaChip is uniquely positioned as a foundry provider to be able to offer the deep trench isolation technology for PMIC applications.
In addition to the PMIC, GMT's LED Driver IC has the ability to drive up to 12 parallel strings of LEDs at a maximum of 120mA of current. It also provides a precision current balance function for each LED string. Additionally, the LED string voltages can be up to a maximum of 65V. This makes it very suitable to be used in main stream (40 inch ~ 55 inch) LED TV back light applications.
Namkyu Park, VP of MagnaChip's Foundry Marketing, commented: "We are very pleased to announce MagnaChip's production ramp of GMT's PMIC products using our 0.35um BCD process technology. The continued introduction of these robust PMIC solutions is a direct result of the combined expertise of MagnaChip's manufacturing services and GMT's design engineering. We will continue to develop highly differentiated and cost-effective BCD technology solutions to meet the increasing application specific needs of our foundry customers."
IDT intros world’s first single-ended multi-output PLL clock generators using pMEMS technology
SAN JOSE, USA: Integrated Device Technology Inc. (IDT) has announced the world’s first low-power, multi-output PLL clock generators using IDT’s patented Piezoelectric MEMS (pMEMS) technology.
The new devices expand IDT’s leading timing portfolio by consolidating the function of two crystal oscillators, completely eliminating the need for external crystals and oscillators. This enables customers to significantly simplify their designs and reduce the bill-of-materials (BOM) in a myriad of general purpose applications, including industrial, cloud computing and mobile.
The IDT5V8001x and IDT5V8002x families are high-performance single- and dual-output ±50 ppm timing devices incorporating IDT’s CrystalFree pMEMS resonators. Combined with IDT’s ultra-low-power PLL technology, this family of devices provides two independent single-ended output frequencies at up to 200 MHz, allowing system designers to reduce component count, save board space, simplify trace routing, and lower testing costs.
The multi-output devices consume up to 75 percent less power than competitive two-output spread spectrum-enabled MEMS timing solutions, making them well-suited for battery-powered portable devices or cooling-hungry enterprise datacenters. These pMEMS-based clock generators offer superb reliability in standard 3x3 mm QFN packaging and operate across the full industrial temperature range.
“Our new CrystalFree pMEMS-based clock generators redefine the standard for high-performance, easy-to-use timing solutions and grow IDT’s portfolio of products and technologies that address the $4B frequency control market,” said Fred Zust, VP and GM of the Timing and Synchronization Division at IDT. “By eliminating the crystal and integrating the PLLs, we’ve taken the ambiguity out of building a timing solution, and consolidated the outputs into a single device with a smaller footprint. Our growing pMEMS portfolio further strengthens our leadership position in timing and delivers the highest level of innovation to advance our customers’ next-generation designs.”
Some of the new clock generator devices feature spread spectrum capability that can be toggled using hardware select pins, allowing the designer to reduce electro-magnetic interference (EMI) in-system during compliance testing, rather than redesigning the whole board. In addition, the devices operate with only 75 ps of short-term cycle-cycle jitter, meeting the demands of high-performance PC and consumer markets.
The IDT IDT5V8001x and IDT5V8002x families are currently sampling to select customers.
The new devices expand IDT’s leading timing portfolio by consolidating the function of two crystal oscillators, completely eliminating the need for external crystals and oscillators. This enables customers to significantly simplify their designs and reduce the bill-of-materials (BOM) in a myriad of general purpose applications, including industrial, cloud computing and mobile.
The IDT5V8001x and IDT5V8002x families are high-performance single- and dual-output ±50 ppm timing devices incorporating IDT’s CrystalFree pMEMS resonators. Combined with IDT’s ultra-low-power PLL technology, this family of devices provides two independent single-ended output frequencies at up to 200 MHz, allowing system designers to reduce component count, save board space, simplify trace routing, and lower testing costs.
The multi-output devices consume up to 75 percent less power than competitive two-output spread spectrum-enabled MEMS timing solutions, making them well-suited for battery-powered portable devices or cooling-hungry enterprise datacenters. These pMEMS-based clock generators offer superb reliability in standard 3x3 mm QFN packaging and operate across the full industrial temperature range.
“Our new CrystalFree pMEMS-based clock generators redefine the standard for high-performance, easy-to-use timing solutions and grow IDT’s portfolio of products and technologies that address the $4B frequency control market,” said Fred Zust, VP and GM of the Timing and Synchronization Division at IDT. “By eliminating the crystal and integrating the PLLs, we’ve taken the ambiguity out of building a timing solution, and consolidated the outputs into a single device with a smaller footprint. Our growing pMEMS portfolio further strengthens our leadership position in timing and delivers the highest level of innovation to advance our customers’ next-generation designs.”
Some of the new clock generator devices feature spread spectrum capability that can be toggled using hardware select pins, allowing the designer to reduce electro-magnetic interference (EMI) in-system during compliance testing, rather than redesigning the whole board. In addition, the devices operate with only 75 ps of short-term cycle-cycle jitter, meeting the demands of high-performance PC and consumer markets.
The IDT IDT5V8001x and IDT5V8002x families are currently sampling to select customers.
X-FAB to exhibit foundry solutions for designers of power electronics at APEC conference and expo
ORLANDO, USA: X-FAB Silicon Foundries, the leading analog/mixed-signal foundry and expert in “More than Moore” technologies, will present its high-performance power management solutions in 0.18 and 0.35 micrometer technologies, in Booth #328 at the APEC Conference and Exposition here, Feb. 6-8, 2012. These solutions are ideal for applications such as precision analog, light source driving, battery management and power systems on chip (SoCs).
X-FAB also will discuss its latest foundry process, XP018, with the industry’s lowest mask count for the modular combination of digital, analog and high-voltage features with embedded Flash. This unique foundry offering for energy-efficient applications is the first to allow SoC integration requiring up to 60V operating voltage with low Rdson and 5V power supply to be combined with embedded non-volatile memory (NVM). It enables a new generation of reliable and efficient power management, digital control and other power-control SoC applications.
X-FAB also will discuss its latest foundry process, XP018, with the industry’s lowest mask count for the modular combination of digital, analog and high-voltage features with embedded Flash. This unique foundry offering for energy-efficient applications is the first to allow SoC integration requiring up to 60V operating voltage with low Rdson and 5V power supply to be combined with embedded non-volatile memory (NVM). It enables a new generation of reliable and efficient power management, digital control and other power-control SoC applications.
ST unveils industry-first car-door controller IC with integrated window control
GENEVA, SWITZERLAND: STMicroelectronics has introduced the market’s first multi-functional door-zone driver with an integrated electric-window control. This innovative chip, which reduces bill-of-material costs and offers new levels of passenger comfort, has already been selected for broad adoption at a leading German car manufacturer.
Today, equipment manufacturers use relays to drive the electric-window motors. ST’s newest door actuator driver redefines the established system topology, removing the need for mechanical relays in car-window control. The innovation slashes component costs and eliminates expensive electromagnetic compatibility (EMC) countermeasures, associated with the existing solutions, while enabling users to enjoy a smoother and quieter car-window operation. ST’s new door-zone driver supports adjustable window speeds related to the position of the window - soft start and shutdown - and reduces noise levels with the removal of the relay as well.
ST’s L99DZ80 embeds an SPI-programmable slew-rate control IP that can drive 4 external MOSFETs in a half-bridge configuration dedicated to PWM (Pulse Width Mode)-driven electric-window applications. Other features include six bridges for double door-lock control, mirror fold, and mirror-axis control, together with a high-side driver for mirror defroster, bulbs and LEDs. The device also integrates a control block with an external MOS transistor for charging and discharging of electrochromic (dimmable) mirror glasses.
ST is the world’s largest supplier of car-door electronics, with more than 100 million door-actuator devices shipped over the past ten years. Designed for state-of-the-art automotive door-module applications, ST’s market-proven devices are renowned and recognized for their scalability, small size, advanced power-management functionality, and superior thermal performance.
The newest addition to ST’s family of microcontroller-driven multi-functional car-door actuator drivers, the L99DZ80 is available in volumes.
Today, equipment manufacturers use relays to drive the electric-window motors. ST’s newest door actuator driver redefines the established system topology, removing the need for mechanical relays in car-window control. The innovation slashes component costs and eliminates expensive electromagnetic compatibility (EMC) countermeasures, associated with the existing solutions, while enabling users to enjoy a smoother and quieter car-window operation. ST’s new door-zone driver supports adjustable window speeds related to the position of the window - soft start and shutdown - and reduces noise levels with the removal of the relay as well.
ST’s L99DZ80 embeds an SPI-programmable slew-rate control IP that can drive 4 external MOSFETs in a half-bridge configuration dedicated to PWM (Pulse Width Mode)-driven electric-window applications. Other features include six bridges for double door-lock control, mirror fold, and mirror-axis control, together with a high-side driver for mirror defroster, bulbs and LEDs. The device also integrates a control block with an external MOS transistor for charging and discharging of electrochromic (dimmable) mirror glasses.
ST is the world’s largest supplier of car-door electronics, with more than 100 million door-actuator devices shipped over the past ten years. Designed for state-of-the-art automotive door-module applications, ST’s market-proven devices are renowned and recognized for their scalability, small size, advanced power-management functionality, and superior thermal performance.
The newest addition to ST’s family of microcontroller-driven multi-functional car-door actuator drivers, the L99DZ80 is available in volumes.
MStar licenses ARM Mali GPU technology for smart-TV apps
CAMBRIDGE, UK: ARM announced that MStar, a leading semiconductor supplier for display and digital home solutions, has licensed ARM Mali Graphics Processing Unit (GPU) technology for use in smart-TV applications.
Already highly integrated into existing MStar products and deployed in the latest mainstream consumer electronics devices, the Mali-400 MP GPU strengthens MStar's industry-leading smart-TV solutions. This includes support for high performance applications, such as the latest 3D user interfaces and gaming experiences.
The deepening relationship between MStar and ARM aims to drive technology innovation between the two companies and alignment on future product roadmaps. User experience is a particular focus as Mali GPU technology is able to provide high-resolution, anti-aliased image quality.
"As a pioneer in the digital home applications space, MStar aims to work with the best partners and the cutting edge technologies they provide," commented WK Chia, VP of R&D, MStar. "Our co-operation with ARM is proving successful, with the Mali-400 GPU in mass production as a key component of the MStar smart-TV system-on-chip (SoC). Seamless support from partners, such as ARM, allows MStar to continue to provide customers with best-in-class solutions and further strengthens our leadership position."
"As consumers demand an improved user experience, one of the challenges will be to provide high quality graphics on all screen sizes," said Pete Hutton, GM of the media processing division, ARM. "Companies, such as MStar are responding to the needs of consumers and the OEMs that supply devices by introducing innovative SoCs based on ARM Mali GPU technology. ARM is proud to be working with MStar as a partner that is driving innovation in consumer markets, such as smart-TVs."
Already highly integrated into existing MStar products and deployed in the latest mainstream consumer electronics devices, the Mali-400 MP GPU strengthens MStar's industry-leading smart-TV solutions. This includes support for high performance applications, such as the latest 3D user interfaces and gaming experiences.
The deepening relationship between MStar and ARM aims to drive technology innovation between the two companies and alignment on future product roadmaps. User experience is a particular focus as Mali GPU technology is able to provide high-resolution, anti-aliased image quality.
"As a pioneer in the digital home applications space, MStar aims to work with the best partners and the cutting edge technologies they provide," commented WK Chia, VP of R&D, MStar. "Our co-operation with ARM is proving successful, with the Mali-400 GPU in mass production as a key component of the MStar smart-TV system-on-chip (SoC). Seamless support from partners, such as ARM, allows MStar to continue to provide customers with best-in-class solutions and further strengthens our leadership position."
"As consumers demand an improved user experience, one of the challenges will be to provide high quality graphics on all screen sizes," said Pete Hutton, GM of the media processing division, ARM. "Companies, such as MStar are responding to the needs of consumers and the OEMs that supply devices by introducing innovative SoCs based on ARM Mali GPU technology. ARM is proud to be working with MStar as a partner that is driving innovation in consumer markets, such as smart-TVs."
Friday, January 27, 2012
Silicon Line announces world’s first optical embedded DisplayPort ICs for notebooks, ultrabooks and tablets
MUNICH, GERMANY: Silicon Line GmbH, a leading provider of ultra-low power analog ICs, has brought to market the SL82728 and SL82718 ICs targeted at notebooks, ultrabooks and tablets using the latest VESA based Embedded DisplayPort standard. The ICs are used to optically connect the graphics processor to the display and enable the replacement of traditional electrical connectors with optical connectors.
Strong consumer demand for high resolution retina type displays and 3D technology is driving the data rates inside mobile devices ever higher. These extremely high data rates not only generate significant EMI when traditional electrical cables are used to transport the data but also are reaching the limits of the practical capabilities of electrical cables.
Silicon Line already has a broad portfolio of ultra-low power high speed optical link interface ICs including products for MIPI D-PHY and MIPI M-PHY based smart phones. The SL82728 and SL82718 are the latest additions to the portfolio and are the first products compliant with the Embedded DisplayPort specification. These world’s first optical Embedded DisplayPort ICs enable Silicon Line to support the latest trends for high performance displays in notebooks, ultrabooks and tablets.
“The latest generation of retina type displays demand extremely high data rates”, says Ian Jackson, senior manager, Sales and Marketing, Silicon Line. “As an example, a 10 inch tablet display with 500 pixels per inch can require up to 23 Gbps and when used in 3D mode would require twice that bandwidth. Optical transport of these signals solves the EMI challenges which these data rates create as well as enabling the small and thin form factor designs specified for Ultrabooks”, he added.
The SL82728 quad channel vertical cavity surface emitting laser (VCSEL) driver and the SL82718 quad channel transimpedance amplifier (TIA) together with appropriate photonics are used to implement an optical link for transporting high speed Embedded DisplayPort signals from the graphics processor to the display.
The devices support up to four data lanes at up to 6 Gbps per lane. They can therefore be used to implement the Embedded DisplayPort Version 1.3 standard which specifies a maximum of 5.4 Gbps per data lane. Their ultra-low power consumption of less than 13 mW per channel at 6 Gbps makes them ideal for mobile battery operated consumer devices such as notebooks, ultrabooks and tablets. Extremely small optical links based on these ICs eliminate EMI issues and enable slim form factor designs.
Single and dual channel versions of these products are also available for applications which require less than four data lanes. The SL82728 and SL82718 are available as bare die and are sampling now.
Strong consumer demand for high resolution retina type displays and 3D technology is driving the data rates inside mobile devices ever higher. These extremely high data rates not only generate significant EMI when traditional electrical cables are used to transport the data but also are reaching the limits of the practical capabilities of electrical cables.
Silicon Line already has a broad portfolio of ultra-low power high speed optical link interface ICs including products for MIPI D-PHY and MIPI M-PHY based smart phones. The SL82728 and SL82718 are the latest additions to the portfolio and are the first products compliant with the Embedded DisplayPort specification. These world’s first optical Embedded DisplayPort ICs enable Silicon Line to support the latest trends for high performance displays in notebooks, ultrabooks and tablets.
“The latest generation of retina type displays demand extremely high data rates”, says Ian Jackson, senior manager, Sales and Marketing, Silicon Line. “As an example, a 10 inch tablet display with 500 pixels per inch can require up to 23 Gbps and when used in 3D mode would require twice that bandwidth. Optical transport of these signals solves the EMI challenges which these data rates create as well as enabling the small and thin form factor designs specified for Ultrabooks”, he added.
The SL82728 quad channel vertical cavity surface emitting laser (VCSEL) driver and the SL82718 quad channel transimpedance amplifier (TIA) together with appropriate photonics are used to implement an optical link for transporting high speed Embedded DisplayPort signals from the graphics processor to the display.
The devices support up to four data lanes at up to 6 Gbps per lane. They can therefore be used to implement the Embedded DisplayPort Version 1.3 standard which specifies a maximum of 5.4 Gbps per data lane. Their ultra-low power consumption of less than 13 mW per channel at 6 Gbps makes them ideal for mobile battery operated consumer devices such as notebooks, ultrabooks and tablets. Extremely small optical links based on these ICs eliminate EMI issues and enable slim form factor designs.
Single and dual channel versions of these products are also available for applications which require less than four data lanes. The SL82728 and SL82718 are available as bare die and are sampling now.
ST's innovative chip enables greater storage capacity and faster multimedia access on portable devices
INDIA: STMicroelectronics introduced the industry’s first voltage-level translator compliant with the latest SD (Secure Digital) 3.0 standard. The increase in storage capacity and access speed of SD 3.0, together with the low static power consumption and small package size of ST’s new level translator, makes it an ideal choice for interfacing application processors or digital basebands to SD memory cards in mobile phones, portable media players, tablets, digital cameras or personal navigation devices.
The SD 3.0 specification provides up to 2 terabytes of storage capacity and accelerates SD interface read/write speeds to 50 megabytes per second, at 50 MHz Double Data Rate. ST’s newest voltage-level translator is the first device on the market to support the new standard, giving system designers a head start in developing portable applications with increased storage space and faster access to multimedia content, including music, videos and pictures.
The ST6G3244 couples high-speed operation with very low power dissipation, supported with the Power Down mode. Data integrity is secured through balanced propagation delays and electromagnetic-interference filters and signal conditioning. Recommended for portable devices that connect directly to the external memory card, ST’s newest voltage-level translator incorporates 15kV air-gap electrostatic discharge protection on the card side.
ST’s selectable-supply (1.8V or 2.9V), 6-bit bi-directional CMOS-level translator for SD, mini-SD and micro-SD memory cards is offered in a space-saving BGA25 package, reducing board area by more than 50 percent over current-generation devices (ST6G3238). It is backward pin-to-pin compatible with most existing SD 2.0 products, so customers can easily ‘hot swap’ and protect their investment in application development. The ST6G3244 is available in volumes, with unit pricing at $0.84 in quantities of 1,000 pieces.
The SD 3.0 specification provides up to 2 terabytes of storage capacity and accelerates SD interface read/write speeds to 50 megabytes per second, at 50 MHz Double Data Rate. ST’s newest voltage-level translator is the first device on the market to support the new standard, giving system designers a head start in developing portable applications with increased storage space and faster access to multimedia content, including music, videos and pictures.
The ST6G3244 couples high-speed operation with very low power dissipation, supported with the Power Down mode. Data integrity is secured through balanced propagation delays and electromagnetic-interference filters and signal conditioning. Recommended for portable devices that connect directly to the external memory card, ST’s newest voltage-level translator incorporates 15kV air-gap electrostatic discharge protection on the card side.
ST’s selectable-supply (1.8V or 2.9V), 6-bit bi-directional CMOS-level translator for SD, mini-SD and micro-SD memory cards is offered in a space-saving BGA25 package, reducing board area by more than 50 percent over current-generation devices (ST6G3238). It is backward pin-to-pin compatible with most existing SD 2.0 products, so customers can easily ‘hot swap’ and protect their investment in application development. The ST6G3244 is available in volumes, with unit pricing at $0.84 in quantities of 1,000 pieces.
MagnaChip to acquire Dawin Electronics
SEOUL, SOUTH KOREA & CUPERTINO, USA: MagnaChip Semiconductor Corp. announced that its Korean subsidiary has entered into a definitive agreement to acquire Dawin Electronics Co. Ltd, a privately held semiconductor company that designs and manufactures Insulated Gate Bipolar Transistor (IGBT), Fast Recovery Diode (FRD) and MOSFET modules. Dawin Electronics is headquartered in Incheon, South Korea, and has
sales offices in China and Europe. Terms of the deal were not disclosed.
"The acquisition of Dawin Electronics is a strategic fit for MagnaChip and allows us to continue to diversify and expand our fast-growing Power Solutions business into the commercial and industrial segments," said Sang Park, MagnaChip's chairman and CEO. "Dawin's high-power modules will enable MagnaChip to compete quickly and effectively in the high-growth IGBT market with a broader portfolio of power solutions for our customers. This acquisition also demonstrates our continued focus on capital allocation and commitment to return shareholder value to our investors."
According to market research firm IHS iSuppli, the total IGBT market in 2011 was estimated to be $4.1 billion and is expected to grow at a compounded annual growth rate of 10 percent from 2011 to 2015. The IGBT is used in a broad range of medium- to high-power commercial and industrial applications and in many consumer appliances such as variable speed refrigerators, air-conditioners and stereo systems.
Availability of affordable, reliable IGBTs is also an important enabler for electric vehicles and hybrid cars.
The acquisition of Dawin and its IGBT and FRD module technology is synergistic with MagnaChip's goal of expanding into high-growth, high-margin markets and with its long history as a designer and manufacturer of analog and mixed-signal semiconductor products. The acquisition is expected to be completed before the end of March 2012.
sales offices in China and Europe. Terms of the deal were not disclosed.
"The acquisition of Dawin Electronics is a strategic fit for MagnaChip and allows us to continue to diversify and expand our fast-growing Power Solutions business into the commercial and industrial segments," said Sang Park, MagnaChip's chairman and CEO. "Dawin's high-power modules will enable MagnaChip to compete quickly and effectively in the high-growth IGBT market with a broader portfolio of power solutions for our customers. This acquisition also demonstrates our continued focus on capital allocation and commitment to return shareholder value to our investors."
According to market research firm IHS iSuppli, the total IGBT market in 2011 was estimated to be $4.1 billion and is expected to grow at a compounded annual growth rate of 10 percent from 2011 to 2015. The IGBT is used in a broad range of medium- to high-power commercial and industrial applications and in many consumer appliances such as variable speed refrigerators, air-conditioners and stereo systems.
Availability of affordable, reliable IGBTs is also an important enabler for electric vehicles and hybrid cars.
The acquisition of Dawin and its IGBT and FRD module technology is synergistic with MagnaChip's goal of expanding into high-growth, high-margin markets and with its long history as a designer and manufacturer of analog and mixed-signal semiconductor products. The acquisition is expected to be completed before the end of March 2012.
Mentor Graphics hires industry veteran in Noida
WILSONVILLE, USA: Mentor Graphics Corp. announced the hiring of industry veteran Dr. Srinivas Mandavilli as Product Line Director for the Integrated Silicon Systems (ISS) business unit with responsibility for a wide breadth of FPGA design products including synthesis and FPGA/PCB co-design.
The addition of Dr. Mandavilli and establishment of the ISS R&D organization in India emphasizes the Mentor Graphics commitment to support FPGA design and its importance to the development of advanced electronic products. Dr. Mandavilli will report directly to Henry Potts, Mentor VP and GM of the Systems Design Division, responsible for approximately 30 percent of the Mentor business.
Dr. Mandavilli has held engineering and management positions in the past at Motorola, Hitachi, and Ionic Microsystems, and was co-founder of Lucivid Software Systems. He also had seven years at Mentor Graphics where he managed the Hyderabad R&D center with engineering management responsibility spanning several areas of advanced technology development. Along with a best thesis award for his Ph.D dissertation in Genetic Algorithms, Srinivas has over 2,000 citations to date for his IEEE publications.
“It is a pleasure to have Srinivas back with Mentor,” stated Henry Potts. “FPGA design and optimization is a critical part of advanced systems design for our customers and the focus on those products, with this investment in India, will ensure their success in the marketplace.”
The addition of Dr. Mandavilli and establishment of the ISS R&D organization in India emphasizes the Mentor Graphics commitment to support FPGA design and its importance to the development of advanced electronic products. Dr. Mandavilli will report directly to Henry Potts, Mentor VP and GM of the Systems Design Division, responsible for approximately 30 percent of the Mentor business.
Dr. Mandavilli has held engineering and management positions in the past at Motorola, Hitachi, and Ionic Microsystems, and was co-founder of Lucivid Software Systems. He also had seven years at Mentor Graphics where he managed the Hyderabad R&D center with engineering management responsibility spanning several areas of advanced technology development. Along with a best thesis award for his Ph.D dissertation in Genetic Algorithms, Srinivas has over 2,000 citations to date for his IEEE publications.
“It is a pleasure to have Srinivas back with Mentor,” stated Henry Potts. “FPGA design and optimization is a critical part of advanced systems design for our customers and the focus on those products, with this investment in India, will ensure their success in the marketplace.”
NVIDIA launches India’s first GPU computing social networking group
BANGALORE, INDIA: NVIDIA announced the launch of an online platform dedicated to GPU computing and High Performance Computing (HPC) users in India. The informal special interest group will bring together GPU users from all fields and experience levels in India, including academicians, researchers, scientists, device manufacturers, system integrators, service providers and all early adopters of HPC and GPU computing.
The group, hosted on Meetup.com – the world's largest network of local groups, will provide HPC and GPU computing enthusiasts in India a comprehensive platform to track industry trends and engage with each other, discussing the latest developments in the field.
The group, supported by NVIDIA, will have a core group of key academicians to lead and moderate discussions. The site will feature a bank of research papers, case studies and posts on the latest technological developments not only at NVIDIA but also in the global industry. The platform will also encourage users to engage over group chats and web conferences to interact with each other. NVIDIA will periodically host live talks with industry experts to elucidate on pertinent industry updates.
Vishal Dhupar, MD, South Asia, NVIDIA, said: “GPU computing is becoming increasingly relevant in our lives today. Everyone from gaming enthusiasts, to college students, working professionals to researchers and scientists can apply the GPU to enable better graphics and faster computing. NVIDIA will lead and facilitate the pioneering HPC and GPU Computing Group with an aim to establish a strong connect among GPU computing users and spread GPU computing awareness in India. We hope to make the GPU synonymous with computing and build a strong interconnected community of GPU users in India.”
HPC and GPU computing has come into sharp focus in India with the Indian Government’s focus on setting-up of Petaflop-class systems in the upcoming five-year plan. NVIDIA will facilitate the virtual informal special interest group as an extension of its University and Academic programs. NVIDIA in India has four different programs to engage with academia, through which 18 CUDA Teaching Centers, 1 CUDA Research Centre and 66 Academic partnership programs have been established in association with universities and professors.
Jaya Panvalkar, senior director and site leader, Pune Design Center, Head – Academic Relationships in NVIDIA India, said: “With NVIDIA’s drive to build stronger ecosystem in academia in India by collaborating with educational and research institutes across the country we are reinforcing NVIDIA’s commitment to developing and building a strong ecosystem of GPU computing in India. NVIDIA’s initiatives with academic and research institutes in the country enables the growth of software developers, scientists and researchers in various engineering and scientific streams. We see this special interest online platform as furthering this growth and bringing in a higher level of excellence in the professional and scientific fields.”
The group, hosted on Meetup.com – the world's largest network of local groups, will provide HPC and GPU computing enthusiasts in India a comprehensive platform to track industry trends and engage with each other, discussing the latest developments in the field.
The group, supported by NVIDIA, will have a core group of key academicians to lead and moderate discussions. The site will feature a bank of research papers, case studies and posts on the latest technological developments not only at NVIDIA but also in the global industry. The platform will also encourage users to engage over group chats and web conferences to interact with each other. NVIDIA will periodically host live talks with industry experts to elucidate on pertinent industry updates.
Vishal Dhupar, MD, South Asia, NVIDIA, said: “GPU computing is becoming increasingly relevant in our lives today. Everyone from gaming enthusiasts, to college students, working professionals to researchers and scientists can apply the GPU to enable better graphics and faster computing. NVIDIA will lead and facilitate the pioneering HPC and GPU Computing Group with an aim to establish a strong connect among GPU computing users and spread GPU computing awareness in India. We hope to make the GPU synonymous with computing and build a strong interconnected community of GPU users in India.”
HPC and GPU computing has come into sharp focus in India with the Indian Government’s focus on setting-up of Petaflop-class systems in the upcoming five-year plan. NVIDIA will facilitate the virtual informal special interest group as an extension of its University and Academic programs. NVIDIA in India has four different programs to engage with academia, through which 18 CUDA Teaching Centers, 1 CUDA Research Centre and 66 Academic partnership programs have been established in association with universities and professors.
Jaya Panvalkar, senior director and site leader, Pune Design Center, Head – Academic Relationships in NVIDIA India, said: “With NVIDIA’s drive to build stronger ecosystem in academia in India by collaborating with educational and research institutes across the country we are reinforcing NVIDIA’s commitment to developing and building a strong ecosystem of GPU computing in India. NVIDIA’s initiatives with academic and research institutes in the country enables the growth of software developers, scientists and researchers in various engineering and scientific streams. We see this special interest online platform as furthering this growth and bringing in a higher level of excellence in the professional and scientific fields.”
AMD upbeat on FirePro professional graphics
NEW DELHI, INDIA: AMD announced its strategic alliance with TAG (Technology And Gadgets), a fast growing national distributor, for the distribution of its entire portfolio of AMD professional graphics including its newest generation of AMD FirePro professional graphics in India.
Through this arrangement with TAG, one of the largest distributors of technology products and accessories, with branches in Ahmedabad, Bangalore, Chennai, Delhi, Hyderabad, Pune and Mumbai, AMD aims to expand its presence in India and explore newer market segments for its professional graphic cards business.
With the explosion in multimedia and the growing importance of visual computing, the Graphics Processor Unit (GPU) and its massively parallel computing architecture is increasingly being leveraged by applications to manage and manipulate data. This is leading to the rapid adoption of latest technologies in the world of graphics not just in the field of entertainment, but other areas like education, retail, mission critical applications and other professional purposes – thereby representing huge business opportunity for AMD FireProTM professional graphics.
“AMD FirePro is one of the fastest growing lines of professional graphic cards," said Ed Caracappa - director of Global Sales, Professional Graphics, AMD. “From generation to generation of graphics performance, this success stems from our unwavering focus on the needs of the professional, where we offer a complete range of professional graphics solutions. We're pleased with the new relationship between AMD and TAG, as it enhances our route to market and gives us the leverage to expand our customer base in India, by adding to our existing base of consumers and entering new geographic segments where TAG has a strong foothold.”
“In the business for a little over 4 years, we take pride over our penetration in nationwide distribution that makes us one of the few specialized value added Video Graphics Array (VGA) distribution houses in India that caters to both consumers and professional segments of the VGA arena. AMD professional graphics cards here represent a high-growth, high-margin sales and service opportunity for our channel partners and growing IT components business, we therefore value our new-found relationship with AMD.” said Vikas Gupta, director, TAG (Technology And Gadget).
“This alliance adds to our business expertise and network and thereby gives us the ability to set new and competitive price barriers for our wide range of offerings that span over 100 products for both desktops and laptops.”
TAG and AMD share the philosophy to bring innovative solutions to market that provide an easier and more profitable way for channel partners and OEMs to deploy and manage business and therefore foresee this relationship as a key milestone in the expansion of professional graphics business in India.
Through this arrangement with TAG, one of the largest distributors of technology products and accessories, with branches in Ahmedabad, Bangalore, Chennai, Delhi, Hyderabad, Pune and Mumbai, AMD aims to expand its presence in India and explore newer market segments for its professional graphic cards business.
With the explosion in multimedia and the growing importance of visual computing, the Graphics Processor Unit (GPU) and its massively parallel computing architecture is increasingly being leveraged by applications to manage and manipulate data. This is leading to the rapid adoption of latest technologies in the world of graphics not just in the field of entertainment, but other areas like education, retail, mission critical applications and other professional purposes – thereby representing huge business opportunity for AMD FireProTM professional graphics.
“AMD FirePro is one of the fastest growing lines of professional graphic cards," said Ed Caracappa - director of Global Sales, Professional Graphics, AMD. “From generation to generation of graphics performance, this success stems from our unwavering focus on the needs of the professional, where we offer a complete range of professional graphics solutions. We're pleased with the new relationship between AMD and TAG, as it enhances our route to market and gives us the leverage to expand our customer base in India, by adding to our existing base of consumers and entering new geographic segments where TAG has a strong foothold.”
“In the business for a little over 4 years, we take pride over our penetration in nationwide distribution that makes us one of the few specialized value added Video Graphics Array (VGA) distribution houses in India that caters to both consumers and professional segments of the VGA arena. AMD professional graphics cards here represent a high-growth, high-margin sales and service opportunity for our channel partners and growing IT components business, we therefore value our new-found relationship with AMD.” said Vikas Gupta, director, TAG (Technology And Gadget).
“This alliance adds to our business expertise and network and thereby gives us the ability to set new and competitive price barriers for our wide range of offerings that span over 100 products for both desktops and laptops.”
TAG and AMD share the philosophy to bring innovative solutions to market that provide an easier and more profitable way for channel partners and OEMs to deploy and manage business and therefore foresee this relationship as a key milestone in the expansion of professional graphics business in India.
Thursday, January 26, 2012
ISCUG 2012: Call for contributions
BANGALORE, INDIA: The Indian SystemC User’s Group (ISCUG) aims to accelerate the adoption of SystemC in the Semiconductor Industry. ISCUG provides a platform for the SystemC beginners, SystemC experts, ESL managers and ESL vendors to share their knowledge, experiences and best practices about SystemC usage. The organizers are calling for contributions to ISCUG 2012 to be held Monday, April 9, 2012 in Bangalore.
Abstract Deadline: Wednesday, 15th Feb 2012
Submit your abstract upto 200 words at: iscug.in/submit_abstract
The final contribution will be a presentation of about 25 minute duration. The topic of the presentation can include all the use cases of SystemC including but not restricted to: Virtual platform for embedded software development, Architectural exploration, Performance optimization, High level synthsis (HLS), Analog Mixed-Signal (AMS) modeling etc. The presentation should not appear like a sales presentation and should not talk about any specific tools/offerings from a ESL vendor.
You may submit the abstract for the following category of sessions:
Getting started with SystemC
The target audience of this session will be the engineers who want to get started with SystemC modelling. The session will consist of one presentation of 50 minute duration or the two presentations of 25 minutes each.
Advanced modelling techniques
This session is for power users of SystemC to share their knowledge and experiences with the industry peers. The session will consist of three to four presentations of 25 minutes each.
ESL success story
In the session the semiconductor companies may share their case study about the usage of SystemC in their ESL flow. They will talk about the challenges faces, methodologies/techniques employed, and the success achieved by using SystemC in their flow. The session with consist of two presentations from two different semiconductor companies.
Abstract Deadline: Wednesday, 15th Feb 2012
Submit your abstract upto 200 words at: iscug.in/submit_abstract
The final contribution will be a presentation of about 25 minute duration. The topic of the presentation can include all the use cases of SystemC including but not restricted to: Virtual platform for embedded software development, Architectural exploration, Performance optimization, High level synthsis (HLS), Analog Mixed-Signal (AMS) modeling etc. The presentation should not appear like a sales presentation and should not talk about any specific tools/offerings from a ESL vendor.
You may submit the abstract for the following category of sessions:
Getting started with SystemC
The target audience of this session will be the engineers who want to get started with SystemC modelling. The session will consist of one presentation of 50 minute duration or the two presentations of 25 minutes each.
Advanced modelling techniques
This session is for power users of SystemC to share their knowledge and experiences with the industry peers. The session will consist of three to four presentations of 25 minutes each.
ESL success story
In the session the semiconductor companies may share their case study about the usage of SystemC in their ESL flow. They will talk about the challenges faces, methodologies/techniques employed, and the success achieved by using SystemC in their flow. The session with consist of two presentations from two different semiconductor companies.
RFaxis granted four fundamental patents for disruptive single-chip single die RFeIC technology
IRVINE, USA: RFaxis, a fabless semiconductor company focused on innovative, next-generation Radio Frequency (RF) solutions for the wireless connectivity and cellular mobility markets, has been awarded four patents for its revolutionary single-chip, single-die RF Front-end Integrated Circuit (RFeIC) architecture. These are the fundamental patents among the company’s substantial intellectual property (IP) portfolio which consists of more than 30 patents that have been filed to-date.
The patents are “Radio Frequency Transceiver Front End Circuit with Matching Circuit Voltage Divider,” “Multi Mode Radio Frequency Transceiver Front End Circuit,” “Multi Mode Radio Frequency Transceiver Front End Circuit with Inter-Stage Matching Circuit,” and “Multi Mode Radio Frequency Transceiver Front End Circuit with Inter-Stage Power Divider.”
“Our single-chip, single-die RFeIC architecture is process and materials agnostic, and can be implemented in all semiconductor technologies such as Gallium Arsenide-based HBT, Indium Phosphide-based HEMT, Silicon Germanium-based BiCMOS or pure bulk CMOS,” commented Dr. Oleksandr Gorbachov, CTO of RFaxis.
“We developed and productized our first-generation RFeICs including the RFX2401 for ZigBee and RFX2402 for WLAN using BiCMOS process in 2009. We have since successfully migrated these products to standard bulk CMOS process and are now shipping our second-generation, backwards-compatible products including RFX2401C and RFX2402C. We are in the process of launching several new pure CMOS-based RFeICs that serve major wireless protocols including WLAN 802.11a/b/g/n/ac, Bluetooth, ZigBee/ISM, and markets such as Smart Meters, Wireless Audio/Video and Home Automation, among others.”
“These four fundamental patents provide full protection for our main architecture,” said Mike Neshat, chairman and CEO of RFaxis. “Our disruptive RFeIC technology is now fully patented. We expect to have more patents granted in the coming weeks and months. Combining these patented architectures along with our in-house design methodologies and trade secrets, RFaxis is truly leading the way of ‘Bridging the RF Gap’ for the exponentially-growing wireless industry, as initially envisioned when we started the company four years ago.”
The patents are “Radio Frequency Transceiver Front End Circuit with Matching Circuit Voltage Divider,” “Multi Mode Radio Frequency Transceiver Front End Circuit,” “Multi Mode Radio Frequency Transceiver Front End Circuit with Inter-Stage Matching Circuit,” and “Multi Mode Radio Frequency Transceiver Front End Circuit with Inter-Stage Power Divider.”
“Our single-chip, single-die RFeIC architecture is process and materials agnostic, and can be implemented in all semiconductor technologies such as Gallium Arsenide-based HBT, Indium Phosphide-based HEMT, Silicon Germanium-based BiCMOS or pure bulk CMOS,” commented Dr. Oleksandr Gorbachov, CTO of RFaxis.
“We developed and productized our first-generation RFeICs including the RFX2401 for ZigBee and RFX2402 for WLAN using BiCMOS process in 2009. We have since successfully migrated these products to standard bulk CMOS process and are now shipping our second-generation, backwards-compatible products including RFX2401C and RFX2402C. We are in the process of launching several new pure CMOS-based RFeICs that serve major wireless protocols including WLAN 802.11a/b/g/n/ac, Bluetooth, ZigBee/ISM, and markets such as Smart Meters, Wireless Audio/Video and Home Automation, among others.”
“These four fundamental patents provide full protection for our main architecture,” said Mike Neshat, chairman and CEO of RFaxis. “Our disruptive RFeIC technology is now fully patented. We expect to have more patents granted in the coming weeks and months. Combining these patented architectures along with our in-house design methodologies and trade secrets, RFaxis is truly leading the way of ‘Bridging the RF Gap’ for the exponentially-growing wireless industry, as initially envisioned when we started the company four years ago.”
Cypress’s Tx-Boost feature for TrueTouch touchscreen controllers delivers three times higher signal-to-noise ratio without using digital filters
SAN JOSE, USA: Cypress Semiconductor Corp. unveiled a breakthrough feature for its Gen4 TrueTouch touchscreen controllers that dramatically improves system performance without added cost. Cypress has developed a new proprietary technology based on Gen4’s patent-pending high-voltage Tx drivers.
Tx-Boost extends Gen4’s performance leadership by delivering three times higher signal-to-noise ratio (SNR) than previously possible. This is accomplished without the use of performance-robbing digital filters or external components, enabling manufacturer’s to produce the industry’s thinnest handsets and tablets with low material costs.
The key to excellent touchscreen performance in noisy environments is high SNR. Gen4 already delivers up to four times the raw SNR of the competition through its internally generated 10V Tx circuitry; whereas competitive offerings require customers to use large, expensive, and noisy external switching regulators to generate high-voltage Tx signaling.
The Tx-Boost feature, now available on all TrueTouch Gen4 devices, uses specialized hardware acceleration to triple the already best-in-class SNR of the Gen4 family. This high SNR enables manufacturers to employ sensor-on-lens with direct lamination to displays and in-cell architectures with flawless performance for the thinnest products in the market.
In addition, Tx-Boost efficiently parallelizes multiple operations in hardware, without burdening the CPU with costly digital filtering. This significantly increases Gen4’s scan speed, making the world’s fastest touchscreen controller even faster. These parallel operations also further improve Gen4’s industry-leading power consumption by increasing the amount of idle time during each scan period.
“We understand that touchscreen customers are in highly competitive markets and need constantly improving technology to stay ahead,” said Dhwani Vyas, VP, Cypress’s User Interface Business Unit. “We’re pleased to provide Tx-Boost to enable the industry’s best controller family to extend its leadership against competitive offerings. Customers who have seen this technology in action have been universally impressed.”
Tx-Boost extends Gen4’s performance leadership by delivering three times higher signal-to-noise ratio (SNR) than previously possible. This is accomplished without the use of performance-robbing digital filters or external components, enabling manufacturer’s to produce the industry’s thinnest handsets and tablets with low material costs.
The key to excellent touchscreen performance in noisy environments is high SNR. Gen4 already delivers up to four times the raw SNR of the competition through its internally generated 10V Tx circuitry; whereas competitive offerings require customers to use large, expensive, and noisy external switching regulators to generate high-voltage Tx signaling.
The Tx-Boost feature, now available on all TrueTouch Gen4 devices, uses specialized hardware acceleration to triple the already best-in-class SNR of the Gen4 family. This high SNR enables manufacturers to employ sensor-on-lens with direct lamination to displays and in-cell architectures with flawless performance for the thinnest products in the market.
In addition, Tx-Boost efficiently parallelizes multiple operations in hardware, without burdening the CPU with costly digital filtering. This significantly increases Gen4’s scan speed, making the world’s fastest touchscreen controller even faster. These parallel operations also further improve Gen4’s industry-leading power consumption by increasing the amount of idle time during each scan period.
“We understand that touchscreen customers are in highly competitive markets and need constantly improving technology to stay ahead,” said Dhwani Vyas, VP, Cypress’s User Interface Business Unit. “We’re pleased to provide Tx-Boost to enable the industry’s best controller family to extend its leadership against competitive offerings. Customers who have seen this technology in action have been universally impressed.”
IR’s compact AUIR0815S automotive-qualified gate drive IC shrinks and simplifies power train design in hybrid and electric vehicles
EL SEGUNDO, USA: International Rectifier (IR), a world leader in power management technology, introduced the AUIR0815S automotive-qualified IC featuring very high output current in excess of 10 A to drive large IGBTs or MOSFETs in inverter stages for the power train of hybrid and electrical vehicles.
The AUIR0815S’ very low output impedance and power losses allow operation in harsh and high temperature environments. Typical output resistance is 90 mOhm sink and 180 mOhm source. The device also features negative Vgs driving and continuous on-state capability as a result of an integrated PMOS output in parallel to the high-side pull-up NMOS. The OUTH and OUTL separated outputs allow selection of two different external resistors for charging and discharging the gate essential for controlling EMI and CdV/dT effect in high power motor driver and SMPS applications.
“The AUIR0815 simplifies the design of inverter systems by offering high current drive capability with all of the necessary protection features and qualification requirements for the harsh automotive drive train environment,” said Davide Giacomini, director of Product Management and Applications, IR’s Automotive Products Business Unit.
At low input state on the IN pin, the OUTL is pulled down to VEE, allowing negative gate driving for margination and wide range of IGBT selection. Internal shoot-through prevention logic controls the OUTH and OUTL outputs to avoid simultaneous conduction to optimize dead time delay. In addition, a low current consumption mode can be activated through an LPM input pin, which reduces the IC consumption at the expenses of slower operation delays.
The device is qualified according to AEC-Q100 standards, housed in an industry standard SO-8 package that features an environmentally friendly, lead-free and RoHS compliant bill of materials, and is part of IR’s automotive quality initiative targeting zero defects.
The AUIR0815S’ very low output impedance and power losses allow operation in harsh and high temperature environments. Typical output resistance is 90 mOhm sink and 180 mOhm source. The device also features negative Vgs driving and continuous on-state capability as a result of an integrated PMOS output in parallel to the high-side pull-up NMOS. The OUTH and OUTL separated outputs allow selection of two different external resistors for charging and discharging the gate essential for controlling EMI and CdV/dT effect in high power motor driver and SMPS applications.
“The AUIR0815 simplifies the design of inverter systems by offering high current drive capability with all of the necessary protection features and qualification requirements for the harsh automotive drive train environment,” said Davide Giacomini, director of Product Management and Applications, IR’s Automotive Products Business Unit.
At low input state on the IN pin, the OUTL is pulled down to VEE, allowing negative gate driving for margination and wide range of IGBT selection. Internal shoot-through prevention logic controls the OUTH and OUTL outputs to avoid simultaneous conduction to optimize dead time delay. In addition, a low current consumption mode can be activated through an LPM input pin, which reduces the IC consumption at the expenses of slower operation delays.
The device is qualified according to AEC-Q100 standards, housed in an industry standard SO-8 package that features an environmentally friendly, lead-free and RoHS compliant bill of materials, and is part of IR’s automotive quality initiative targeting zero defects.
GSI reports developments related to pending patent litigation with Cypress
SUNNYVALE, USA: GSI Technology Inc. responded to Cypress Semiconductor Corp.’s January 18, 2012 press release regarding the status of pending patent litigation between the two companies.
Lee-Lean Shu, GSI’s president and CEO, noted: "In its most recent press release, Cypress has once again chosen to make misleading statements in the press rather than fight the lawsuit on the merits before the International Trade Commission (ITC). Their press release states: 'Cypress expands its patent infringement complaint.' In truth," said Shu, "contrary to Cypress’ report, the judge in the ITC proceeding specifically denied Cypress’ request to expand its complaint – Order No. 20: Denying Complainant Cypress Semiconductor Corp.’s Motion for Leave to Amend the Complaint (dated January 4, 2012).
"Further, the only recent order allowing the expansion of the pleadings in the proceeding was an order allowing GSI to amend its responsive pleading – Order No. 22: Granting Respondents’ Motion for Leave to Amend Their Responses to the Second Amended Complaint and Notice of Investigation (dated January 9, 2012).
“The facts are that GSI has had a remarkable series of victories during the pre-trial phase of the ITC proceeding,” continued Shu. "In another recent order, for example, the judge also denied a motion by Cypress that would have expanded the scope of Cypress’ discovery. In addition, the US Patent and Trademark Office (PTO) has issued initial office actions rejecting a number of claims of the Cypress patents as invalid on the basis of prior art, as GSI announced in November."
“It continues to be Cypress’ strategy to attempt to intimidate customers and prospective purchasers of GSI’s technologically superior products by making misleading statements about developments in the patent litigation,” said Didier Lasserre, GSI’s VP of Worldwide Sales. “As the March 2012 trial date approaches, Cypress seems to be ratcheting up these efforts,” he added.
“We remain confident in our position on the merits of the case and look forward to prevailing at the trial in March,” said Shu. “In fact," he added, "on January 19, 2012, we filed motions for summary determination seeking a pre-trial ruling that GSI and the other respondents do not infringe any of the Cypress patents asserted against them.”
Lee-Lean Shu, GSI’s president and CEO, noted: "In its most recent press release, Cypress has once again chosen to make misleading statements in the press rather than fight the lawsuit on the merits before the International Trade Commission (ITC). Their press release states: 'Cypress expands its patent infringement complaint.' In truth," said Shu, "contrary to Cypress’ report, the judge in the ITC proceeding specifically denied Cypress’ request to expand its complaint – Order No. 20: Denying Complainant Cypress Semiconductor Corp.’s Motion for Leave to Amend the Complaint (dated January 4, 2012).
"Further, the only recent order allowing the expansion of the pleadings in the proceeding was an order allowing GSI to amend its responsive pleading – Order No. 22: Granting Respondents’ Motion for Leave to Amend Their Responses to the Second Amended Complaint and Notice of Investigation (dated January 9, 2012).
“The facts are that GSI has had a remarkable series of victories during the pre-trial phase of the ITC proceeding,” continued Shu. "In another recent order, for example, the judge also denied a motion by Cypress that would have expanded the scope of Cypress’ discovery. In addition, the US Patent and Trademark Office (PTO) has issued initial office actions rejecting a number of claims of the Cypress patents as invalid on the basis of prior art, as GSI announced in November."
“It continues to be Cypress’ strategy to attempt to intimidate customers and prospective purchasers of GSI’s technologically superior products by making misleading statements about developments in the patent litigation,” said Didier Lasserre, GSI’s VP of Worldwide Sales. “As the March 2012 trial date approaches, Cypress seems to be ratcheting up these efforts,” he added.
“We remain confident in our position on the merits of the case and look forward to prevailing at the trial in March,” said Shu. “In fact," he added, "on January 19, 2012, we filed motions for summary determination seeking a pre-trial ruling that GSI and the other respondents do not infringe any of the Cypress patents asserted against them.”
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