Mentor Graphics delivers first ARM Cortex and AMBA family verification solution that spans simulation and emulation

WILSONVILLE, USA: Mentor Graphics Corp. announced that its industry-leading Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. This enables both hardware and software engineers to fully verify their multi-core ARM-based designs seamlessly across the Questa verification and Veloce emulation platforms.

The Mentor library of accelerated Instruction Set Simulation (ISS) models that currently includes all ARM Cortex A-family, Cortex R-family, and Cortex M-family processors, has added support for ARM's newest Cortex A7 MPCore and Cortex A15 MPCore products. Multi-core SoC designs incorporating these processors can now be verified across both the Questa and Veloce verification platforms with the Questa Codelink product’s unique ‘DVR-style’ of simulation/emulation playback for debugging.

Engineers can combine their RTL processor models with the ISS processor models, which can be hot-swapped on-the-fly during simulation. This enables engineers to realize the benefits of accelerated simulation, without sacrificing accuracy for debugging.

By making these models portable to the Veloce emulation platform, software and hardware can be verified at even higher speeds, all while enabling off-line debugging, leaving high-in-demand emulators to run even more regression tests.

Mentor has also expanded its library of verification IP (VIP) with the addition of AMBA 4 ACE support to Questa Verification IP. Building on the previously announced support for protocols such as AMBA, DDR, Ethernet and PCI Express, Mentor continues to maintain a comprehensive VIP solution across both simulation and emulation for ARM-based SoCs.

The ACE protocol adds hardware support for cache coherency, bringing benefits in both power and performance, but presenting some unique and complex challenges to verification engineers. Mentor has leveraged industry expertise in verification methodology, including OVM and UVM, AMBA and cache-coherent, multi-processor system verification to deliver the industry’s most comprehensive verification solution for ACE. Engineers can now completely verify and integrate IP supporting ACE quickly and with reduced cost with the comprehensive test, coverage, check and debug capabilities built into the Questa VIP.

“We have worked directly with ARM and mutual customers to put in place verification solutions that enable designers to design and verify next-generation SoCs that leverage ARM’s big.LITTLE processing,” said John Lenyo, GM of Design Verification Technology division of Mentor Graphics. “Our unique Questa and Veloce functional verification platforms, optimized to support multi-core hardware and software verification, enable a new class of SoC-Level Verification that allows our users to deliver on their first-to-market plans.”

The Questa Codelink support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP support for AMBA4 ACE is available immediately.