SpringSoft’s Verdi debug software expands verification interoperability with comprehensive UVM support

HSINCHU, TAIWAN: SpringSoft Inc., a global supplier of specialized IC design software, announced comprehensive support for the Universal Verification Methodology (UVM) with its Verdi Automated Debug System.

The Verdi software adds UVM source code and new transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize and debug the complex SystemVerilog testbench structures required to test sophisticated system-on-chip (SoC) devices.

UVM is becoming an industry standard approach to ensuring the reusability and interoperability of testbench code (also referred to as verification IP) integrated from multiple sources or developed using different methodologies. The Verdi UVM capabilities are enabled within the system’s unified testbench and design debug environment for more efficient recording and viewing of transaction data beyond what is supported by the current UVM infrastructure.

With the ability to visualize a broader range of information between the testbench and design under test at the transaction level, Verdi users have a more complete picture of their environment, which is especially critical during detailed regression testing phases.

“Just as SystemVerilog provides a compelling advantage in addressing verification complexity, UVM provides the infrastructure for greater verification interoperability,” said Thomas Li, director of product marketing at SpringSoft. “Our UVM implementation combines the proven capabilities of Verdi with enhanced UVM transaction recording that extracts more information critical to debug. This gives engineers a more natural way to better understand and analyze testbench activities and determine whether problems originate in the testbench or the design.”