TowerJazz demos advanced design enablement offerings

DATE 2011, MIGDAL HAEMEK, ISRAEL & NEWPORT BEACH, USA: TowerJazz, the global specialty foundry leader, announced that it will demonstrate its advanced design enablement offerings focused on its power management and RF/HPA (high performance analog) process technologies at the 2011 Design Automation and Test in Europe (DATE) conference.

TowerJazz has qualified design flows for its analog/mixed-signal 180nm power management process with several electronic design automation (EDA) vendors including: Agilent Technologies, Cadence Design Systems, Synopsys, Magma Design Automation, Mentor Graphics, and Tanner EDA. TowerJazz will be providing demonstrations with all of these vendors at DATE on March 15-17, 2011 in Grenoble, France. In addition, experts will be available to discuss TowerJazz’s process technology and roadmaps.

TowerJazz provides design kits, IPs and dedicated design services that enable its customers with a quick and accurate design cycle and the best chance for first-time working silicon. TowerJazz has focused its latest design enablement efforts in the emerging power management (PM) area as well as the RF/HPA areas to provide design enablement platforms that complement its advanced technologies. These include custom and unique design tools such as X-Sigma, PCM based modeling, inductor and transmission line synthesis tools that help customers reduce design time and cost.

Specifically, TowerJazz has introduced new technology initiatives to an existing power market that have been widely accepted by its customers. Beyond supporting all the devices of the basic, isolated, and 700V PM platforms, the PDK includes add-ons such as thick top Cu (3.3um) metal for high currents and an add-on layer for 15% Rdson reduction which helps reduce die cost. The designer can also choose between a single gate (5V) and a dual gate (1.8V/5V) option, based on the digital content of the design. This enables the customer to choose whichever option they prefer, functionality vs. cost.

TowerJazz also enabled many power IPs including 5V only standard cell, its unique patented NVM solution called Y-Flash, and IO libraries with Si proven ESD.

Recently, TowerJazz announced the release of its 0.18um power management EPI platform design kit. The kit is an extension of its successful TS18PM platform which includes the industry’s only scalable Rdson versus breakdown voltage LDMOS which enables 10-40% smaller die sizes and faster design cycle times. Another benefit is that it meets the strong noise isolation required by today’s leading power management products.

TowerJazz has also expanded its offering in the RF/HPA product line by enabling an industry leading 250GHz modular platform, allowing existing SiGe BiCMOS customers to re-use their IP and migrate existing designs to lower power or higher-speed versions, or to design new products leveraging the high-speed of a SiGe bipolar device. In addition, TowerJazz released a PDK for a low cost version of its 0.18um SiGe BiCMOS process (SBL18), a Transmission-line-toolbox, Cadence IC6.1 and Agilent ADS versions of the SBC18 PDK. These are enabling its customers to design new products at reduced design time and cost.

A new 0.13um SiGe BiCMOS (TSBL13) PDK is now available with Cu back-end, enabling a 0.13um SiGe NPN to be integrated with RF CMOS functions. This offering is further enriched via the development of several meaningful IP blocks. Finally, TowerJazz licensed Kilopass' One-Time Programmable Non-Volatile Memory (OTP NVM) and ARM’s Low Power Libraries, among others, for its 0.13 SiGe BiCMOS and 0.13um RF CMOS platforms.

“We have the infrastructure to enable our customers the best technology coupled with modular design kits, proven reference flows, custom design and porting tools that provide unmatched flexibility in choosing their EDA & IP vendors,” said Ori Galzur, Vice President of Design Center and PDK Development. “Additionally, our wide variety of IPs enables our customers to concentrate on their design core and enjoy a clean and easy IP integration.”