Open-Silicon enhances Interlaken IP core for very high-speed chip-to-chip serial interfaces

MILPITAS, USA: Open-Silicon Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today the availability of an enhanced version of its Interlaken controller IP core.

The updated core features fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical and physical SerDes lanes provides the flexibility necessary to ease board-level design complexities for very high-speed chip-to-chip serial interfaces.

This latest feature is an evolution of the silicon-proven Open-Silicon Interlaken HiFlex architecture, which has been successfully deployed in multiple ASIC technologies addressing applications from 40Gbps to 300Gbps. The new version also carries forward existing HiFlex features such as Interlaken-LA, In-Band and Out-of-Band flow control, multiple user-interface options, flexible statistics counters and built-in interrupt structures. This controller is fully compliant with the latest Interlaken Protocol Definition (v1.2), the Interlaken Look-Aside Protocol Definition (v1.1), and the Interlaken Interop Recommendations (v1.4).

ASIC Interlaken IP core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology.

Open-Silicon's Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.

The Interlaken protocol is an integral part of today's leading edge data networking products, enabling fast, low latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon's Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors.

This support for multiple industry-leading SerDes PHYs allows Open-Silicon's customers to quickly integrate the core into their technology of choice. "Open-Silicon is focused on providing solutions to help customers get their networking, storage, and computing SoCs to market quickly," said Naveed Sherwani, CEO and president for Open-Silicon.

"From architecture services to software development to this latest generation of our industry-leading Interlaken IP core, Open-Silicon provides comprehensive, flexible solutions for various development models including traditional ASIC design and newer derivative SoC design engagements."