Olympus-ITA 3D-IC metrology system verifies alignment for 3D interconnects in bonded wafers

SEMICON West 2010, SAN JOSE, USA: Olympus Integrated Technologies America Inc. (Olympus-ITA) will present its 3D-IC Automated Metrology System at SEMICON West 2010 in North Hall booth #6047.

The system provides precise imaging technology to verify alignment of bonded wafers and through silicon vias (TSV). Alignment is critical for the device to function optimally.

The 3D interconnect process using TSVs requires bonding the active side of processed wafers together. Once the wafers are bonded there is an immediate need to verify the accuracy of the bonding alignment, but the active wafer surfaces containing the alignment targets are no longer visible.

The Olympus IR 3D-IC Metrology System allows observation and image acquisition of the alignment targets and vias by "seeing” through up to 1200µm of bulk silicon to the patterned surfaces. Overlaid alignment marks are imaged and measured to verify bonding alignment accuracy. IR microscopy is a non-destructive technique, making it especially suited to in-line metrology for the bonded wafer pairs and dies required for 3D interconnects.

"As has been previously presented by Andrew Rudack of SEMATECH, IR microscopy can be used as an early indicator of electrical yield in bonded wafer pairs used for 3D integration," said Greg Baker, Olympus-ITA president. "Overlay metrology using IR microscopy can immediately follow the wafer bonding process and be used to predict yields at this early stage in the 3D interconnect process, providing substantial savings in manufacturing costs."