European expert panel proposes new analog IC design methodology to counter analog bottleneck

SAN JOSE, USA: Global Semiconductor Alliance (GSA), the voice of the global semiconductor industry, recently hosted a panel of European analogue IC design experts at the GSA & IET International Semiconductor Forum in London on 19 May. The discussion led to a possible solution to the analogue IC design bottleneck.

The Global Semiconductor Alliance together with the UK’s Institution of Engineering & Technology joined forces to highlight and discuss European trends in semiconductor development. This year’s program focused on leveraging and maximising European expertise in analogue/mixed-signal, wireless, low-power applications and quality/reliability to access emerging markets for silicon growth including smart cards, power electronics and home networking.

"The panel addressed the problems facing today's analogue designers, including technology and design issues, which are the cause of the analogue bottleneck," explains panel chair Paul Double, GSA’s European chair of the Analogue/Mixed-Signal Interest Group and founder and managing director of EDA Solutions Limited. "The discussion resulted in a proposed new methodology for IC design which leads to faster layout, allowing early analysis of the extracted design," added Double.

Market research indicates that although analogue circuitry comprises only 20 percent of the area in today’s modern mixed-signal devices, it is likely to account for some 80 percent of yield loss.

Due to the complexity of the design and dramatic increase in process related design rules to be considered, mixed-signal design, and especially full custom design, is leading to more errors and performance related problems. Manual design and layout is no longer viable, yet automation in the analogue design world remains difficult, and is often an anathema to analogue designers. This quandary is often referred to as the analogue bottleneck.

The findings of the panel discussion suggested a new approach to analogue design to help offset this bottleneck. Because analogue layout at the deeper process nodes is heavily dependent on processing effects, it often does not make sense to perform simulation before the layout stage as in a traditional IC design flow.

The solution proposed by the panel to achieve faster layout is to allow early analysis of the extracted design. The flow from schematic to layout has to be accelerated, with simulation only after parasitic extraction. This requires a change in CAD methodology to accelerate the manual layout process.

The existing approach is currently: circuit entry in schematic form, simulation, adjust the schematic, re-simulate, repeat until satisfied with simulation and then on to layout and finally, verification of layout. The new approach proposed by the panel is: schematic, directly to layout, verification including extraction of layout complete with parasitics, simulation, then repeat the entire process until simulations are satisfactory.

To support this new methodology, IC design software must feature robust device layout generators, correct by construction placement tools and an integrated router, to enable early analysis and characterisation.

Present on the GSA and IET analogue panel were Ross Addinall, Europe technical director at Ciranova, Peter Frith, chief technical officer of Wolfson Microelectronics, Doug Pattullo, director of Field Technical Support at TSMC Europe and Ciaran Whyte, co-founder and chief technical officer at IC Mask Design.

The panel was chaired and moderated by Paul Double, GSA’s European chair of the Analogue/Mixed-Signal Interest Group and founder and managing director of EDA Solutions Ltd.