CHANDLER & DALLAS, USA: Amkor Technology Inc. and Texas Instruments Inc. (TI) have qualified and begun production of the industry's first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to current solder bump flip chip technology.
Co-developed to lower the packaging costs of integrated circuit (IC) devices with fine pitch input/output (I/O) pad structures of less than 50 microns (um), the proprietary technology platform also boosts performance, making it ideal for wireless and embedded processing applications based on plated copper pillar bumping and assembly technology.
"As chip I/O density increases with each process node, we had to find a way to decrease the distance between pins," said Tom Thorpe, TI vice president and manager of external development and manufacturing (EDM).
"Working together, Amkor and TI rapidly developed, qualified and deployed a new package platform that will not only address TI's flip chip package needs for the next decade but will also serve as a game changer for the industry. This new packaging technology will drive down the size and cost of semiconductors while boosting performance – a win for TI, Amkor and our customers."
"Amkor and TI worked tirelessly to bring this complex technology to market against a challenging development timeline," said Ken Joyce, president and CEO of Amkor Technology.
"Both organizations mobilized significant resources to advance the state of the art for copper pillar bumping, fine pitch interconnect assembly, and advanced packaging. We are committed to partnering with TI in applying this new technology on chip scale packages (CSP), conventional package on package (PoP), and next generation TMV™ PoP configurations."
Fine pitch Flip Chip with copper pillar technologies
This new lead free technology enables the use of flip chip interconnection at fine pad pitches (50 um and smaller) using fine pitch copper pillar bumping and a newly developed assembly process.
Additionally, this technology acts as the platform interconnect technology for integration with next generation advanced silicon nodes.
The fine pitch flip chip layout design methodology typically reduces substrate layer count as compared to standard area array flip chip, yielding a low cost package solution. The fine pitch flip chip package was developed for very thin die, which, when combined with the low standoff height of the copper pillar bump itself, reduces package height.