Toshiba Information Systems (Japan) standardizes on VMM-LP low power verification methodology

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Toshiba Information Systems (Japan) has standardized on the Verification Methodology Manual for Low Power (VMM-LP) to verify its low power chip designs.

Incorporating industry best practices from the collective real-life experiences of more than 30 companies, the VMM-LP provides a framework for accelerating the verification of low power designs. Toshiba Information Systems (Japan) used Synopsys' voltage-aware VCS functional verification solution with MVSIM and VMM-LP to deploy a uniform, structured and repeatable verification methodology across its low power design projects.

Toshiba Information Systems (Japan) performs design and verification services for low power designs with complex low power architectures employing multiple voltage domains and advanced design techniques. The functional modes of the design map to several power modes, and a single undetected bug may cause the entire system to not meet power requirements or to even malfunction.

Verification of all the design's power modes requires a rigorous and methodical approach to ensure bug-free silicon. One of the most time-consuming aspects of low-power verification is the development and deployment of a reusable testbench across multiple projects.

Leveraging the documented methodology in the VMM-LP book and using the low power base classes, Toshiba Information Systems (Japan) was successful in verifying the low power functionality of a mobile multimedia application and setting up a testbench infrastructure that can be quickly adapted to other low power projects.

"We are seeing a rapid increase in the complexity of low power designs in Japan," said Tomoji Takada, general manager, LSI Solutions Division, Toshiba Information Systems (Japan). "In addition to using a voltage-aware verification solution provided by VCS with MVSIM, we needed a structured methodology to enable efficient low-power verification and ensure high-quality designs. VMM-LP provided us this structured methodology. It also helped us to find ways to leverage our verification setup and build upon our verification expertise in OCP and AMBA-based environments and extend it from one low power project to the next."

"VMM-LP addresses the market need for innovation in low power verification," said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys, Inc. "Our collaboration with Toshiba Information Systems (Japan) will help to deploy the VMM-LP methodology on many design projects. Synopsys will continue to invest and collaborate with industry leaders in developing and enabling next-generation verification methodologies."