Arasan Chip Systems hosts panel discussion on Total IP solutions at DesignCon 2010

SAN JOSE, USA: Arasan Chip Systems Inc. is hosting a business panel titled "Total IP Solutions required to Ease SoC Integration" at DesignCon 2010, February 1-4, 2010 at Santa Clara, USA. Arasan will also present a paper on high-performance architectures for Error Correcting Codes (ECC) in NAND memory controller IP.

DesignCon is a premier event bringing together technologists and business executives in the chip design industry. This business panel will consist of semiconductor executives who will present both a provider and consumer perspective. It will be chaired by Ram Gopalan, Senior Director of Marketing at Arasan on February 3, 2010 at the Santa Clara Convention Center.

He observed: "Arasan, with a track record of 15 years in the semiconductor IP business with over 250 licensees, has seen its customers transitioning to a Total IP solutions approach. Gone are the days when a RTL IP database and documentation were sufficient. Now customers demand a consultative approach in selecting and optimizing the IP and additional collateral like vIP, software, hardware tools etc that Arasan provides as part of its Total IP Solutions."

Today's SoC design teams are constrained by the opposing requirements of higher speeds, increased functionality, and reduced time-to-market, shrinking budgets. In this environment, reliance on external IP providers is only increasing. However in order to enable a smooth IP integration path, IP providers have to go beyond providing IP by also provide supporting collateral.

The panelists include IP solution providers as well as SoC Integrators/System Designers who will share their IP integration experience and key requirements from a Total Solution perspective. The panel will provide an insight into these key issues facing their design teams and explore solutions.

In response to these trends, progressive semiconductor IP companies such as Arasan are now providing a Total IP Solution that helps SoC teams succeed in their overall project objectives. This Total IP Solution starts by providing Architectural consulting, and includes Digital IP, Analog IP, Verification IP, Software Drivers/Stacks, Hardware platforms for development and validation, tools like protocol analyzers and professional services/support.

Arasan will also be presenting a technical paper on "Evolving throughput driven architecture for error correction in NAND memory", by Arul K Subbiah, Design Manager at Arasan, scheduled for February 3, 2010. The increase in memory density and interface speed of NAND memory require a higher performance error correction module in memory controllers. This paper shows how Arasan continues to provide innovative NAND memory controller IP cores that scale to meet this challenge.