Cadence OVM SystemVerilog solution enables more thorough verification and reduces costs at Mitsubishi Electric

SAN JOSE, USA: Cadence Design Systems Inc. announced that Mitsubishi Electric Corp. has adopted Cadence verification technology, including a unique adaptation of the Open Verification Methodology (OVM), that has helped cut verification time and improve ASIC product quality.

By deploying the Cadence OVM SystemVerilog module-based solution, Mitsubishi has been able to conduct more thorough verification on its chips while reducing costs.

“This methodology has enabled us to reuse 40 percent of our verification components throughout a series of ASIC developments,” said Yoshimasa Ishino, department manager, LSI Design Engineering Department at Mitsubishi Electric's Design Systems Engineering Center.

“Building and reusing verification components based on OVM makes it easier to focus on the enhancements introduced in the new products. As a result, we were able to reuse our previous verification environment and reduce the time it took us to complete the new environment by 30 percent. We are sure that the Cadence OVM SystemVerilog module-based approach will be an effective way to reduce our resources and costs used for SystemVerilog-based verification.”

The OVM SystemVerilog module-based solution is geared for customers who have not yet moved to an object-oriented verification methodology but still need reuse and scalability. It overlays portions of the OVM library with Verilog modules to provide a simplified user interface to the OVM without affecting the methodology for reuse.

This approach is ideal for design engineers who need to do some verification but are new to the object-oriented programming required for use of the general OVM library. The verification IP (VIP) created with the module-based approach has the same plug-and-play structure as the full class-based OVM approach, thereby simplifying integration .

“We developed this unique adaptation of the OVM because we understood that, while many companies seek the benefits of the OVM, some aren’t prepared quite yet to take the step to object-oriented verification,” said Thomas L. Anderson, product marketing director of Enterprise Verification at Cadence. “The OVM SystemVerilog module-based solution eases adoption of advanced verification while delivering the reuse and scalability needed to conduct cost-efficient, thorough design validation.”