AUSTIN, USA: Freescale Semiconductor’s StarCore SC3850 core technology used in the MSC8156 multicore digital signal processor (DSP), has garnered leading benchmark results from independent signal-processing technology analysis firm, Berkeley Design Technology, Inc. (BDTI).
Specifically, Freescale’s SC3850 1 GHz core registered the highest fixed-point BDTImark2000 score of any DSP architecture tested by BDTI to date.
The BDTImark2000 is one of the industry's most respected measures for DSP performance. The score is distilled from a processor’s results on the BDTI DSP Kernel Benchmarks, which is a suite of key DSP-oriented algorithms. A higher score indicates a faster core or processor.
Freescale’s MSC8156 processor is a six-core device based on SC3850 StarCore DSP core technology and is designed to dramatically advance the capabilities of wireless broadband base station equipment. SC3850 core technology, which populates each of the six cores on the MSC8156 DSP, achieved a BDTImark2000 score of 15420 – the highest score ever certified by BDTI. This score exceeds the BDTImark2000 score of 13170 previously set by Texas Instrument’s 1.2 GHz C64X DSP.
“Freescale is experiencing strong global market traction with the MSC8156 DSP, and several leading OEMs have already adopted the DSP for their newest base station offerings,” said Scott Aylor, general manager of DSP Products for Freescale’s Networking and Multimedia Group. “Now, the widely recognized and respected BDTI score substantiates the innovation and performance levels we’ve been able to achieve with the MSC8156.”
Freescale’s MSC8156 has distinguished itself as a best-in-class DSP by coupling the world's highest-performance DSP cores with innovative on-chip multi-standard forward error correction (FEC) acceleration and Fourier transforms acceleration.
Together with its efficient architecture, highly optimized compiler and state-of-the-art IDE development suite for high-performance embedded signal processing applications, the MSC8156 allows designers to focus on the application, not on removing system-level bottlenecks typically encountered in costly FPGA-based designs and expensive-to-develop ASIC-based designs.
Thursday, January 21, 2010
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