MUMBAI, INDIA: NVIDIA announced the availability of GRID Test Drive, a simple and secure way to test the power of NVIDIA’s GRID technology for cloud-delivered graphics acceleration from almost any location.
The first of its type, GRID Test Drive is now available in India and is being showcased at VMWare’s vForum – one of India’s largest and most influential virtualization, cloud computing and end-user computing conference.
NVIDIA GRID technology allows knowledge workers and high-end graphics users such as engineers and designers to utilize graphics-rich applications through the cloud anywhere on any device – with the same quality and performance they would have on a professional workstation.
NVIDIA GRID provides a critical performance boost for enterprise users in virtualized environments running anything from basic web-based applications like HTML 5 to professional applications such as PTC Creo, Siemens NX and Dassault Systèmes SOLIDWORKS.
Now, with GRID Test Drive, anyone who is interested in experiencing the benefit of graphics acceleration for virtualized desktops can do so immediately without first having to build a proof-of-concept private cloud. GRID Test Drive accelerates user insight into the benefits of virtualized graphics and provides an easy way for any GRID partner to demonstrate GRID technology.
Friday, October 31, 2014
Synopsys announces DesignWare NVM IP for TowerJazz 180-nm process technology
MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of the silicon-proven DesignWare AEON Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP for TowerJazz 180-nanometer (nm) SL process technology.
The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps. The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming.
The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analog IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability.
"It is critical for us to collaborate with an established IP provider who understands our technology needs and is able to deliver high-quality and feature-rich IP solutions quickly," said Soonwon Hong, VP of Leading Division at TLi. "Integrating Synopsys' proven DesignWare AEON FTP Trim NVM IP for the TowerJazz 180-nanometer process technology delivered the area and performance we required, while reducing integration risk and accelerating our time-to-market by three months."
"Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers' aggressive schedule requirements and need for small reprogrammable non-volatile memory IP in the TowerJazz 180-nanometer process technology," said Tal Bar (Dotan), director of IP Design Services at TowerJazz. "The combination of Synopsys' trusted IP solution and TowerJazz's IC manufacturing capabilities helps our mutual customers achieve their design goals faster and with less integration risk."
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customizations and changes.
The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40 degrees C to +125 degrees C) for industrial applications.
"As a leading provider of reprogrammable NVM IP, Synopsys delivers high-quality solutions that enable designers to incorporate the required functionality into their SoCs with less risk," said John Koeter, VP, marketing for IP and prototyping at Synopsys. "With more than four billion customer ICs shipping with DesignWare NVM IP to-date, Synopsys delivers a silicon-proven, fully qualified NVM IP solution for TowerJazz 180-nanometer process technology that helps designers meet their project schedule and accelerate their time to volume."
The DesignWare AEON Trim NVM IP for TowerJazz 180-nm process is available now. DesignWare NVM IP is also available for multiple other foundries in 250-nm to 40-nm process technologies.
The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps. The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming.
The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analog IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability.
"It is critical for us to collaborate with an established IP provider who understands our technology needs and is able to deliver high-quality and feature-rich IP solutions quickly," said Soonwon Hong, VP of Leading Division at TLi. "Integrating Synopsys' proven DesignWare AEON FTP Trim NVM IP for the TowerJazz 180-nanometer process technology delivered the area and performance we required, while reducing integration risk and accelerating our time-to-market by three months."
"Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers' aggressive schedule requirements and need for small reprogrammable non-volatile memory IP in the TowerJazz 180-nanometer process technology," said Tal Bar (Dotan), director of IP Design Services at TowerJazz. "The combination of Synopsys' trusted IP solution and TowerJazz's IC manufacturing capabilities helps our mutual customers achieve their design goals faster and with less integration risk."
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customizations and changes.
The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40 degrees C to +125 degrees C) for industrial applications.
"As a leading provider of reprogrammable NVM IP, Synopsys delivers high-quality solutions that enable designers to incorporate the required functionality into their SoCs with less risk," said John Koeter, VP, marketing for IP and prototyping at Synopsys. "With more than four billion customer ICs shipping with DesignWare NVM IP to-date, Synopsys delivers a silicon-proven, fully qualified NVM IP solution for TowerJazz 180-nanometer process technology that helps designers meet their project schedule and accelerate their time to volume."
The DesignWare AEON Trim NVM IP for TowerJazz 180-nm process is available now. DesignWare NVM IP is also available for multiple other foundries in 250-nm to 40-nm process technologies.
Thursday, October 30, 2014
SEMICON Japan 2014: New venue and new ideas for rebounding industry
TOKYO, JAPAN: SEMI announced an exceptional lineup of speakers for SEMICON Japan’s Opening Day — Accenture, Applied Materials, ARM, IBM Japan, Intel K.K., NIICT, Scripps, Toshiba, and Toyota.
SEMICON Japan 2014, the largest exhibition in Japan for semiconductor manufacturing and related processing technology, will take place at its new venue in Tokyo Big Sight in Tokyo on December 3-5.
A deep program spans from the 33rd annual SEMI Technology Symposium (STS) which begins on December 3, includes sessions on power devices, DFM, lithography, MEMS, packaging, and more to the new World of IoT (Internet of Things).
While the semiconductor and IC manufacturing industries have undergone consolidation, a surge in new investment points to a rebound in related spending in Japan. The semiconductor equipment market in Japan is forecast to grow both in 2014 and 2015.
Drivers for the increased investment are: memory devices, power semiconductors and “More than Moore” semiconductor technologies. According to the SEMI World Fab Forecast, in 2014, Japan will spend more than $10 billion in 2014 on semiconductor equipment and materials. The projection for 2015 is to more than double semiconductor equipment spending to $4.2 billion.
SEMICON Japan 2014 will bring Japan’s rebounding semiconductor equipment market into focus and the underlying technology and business drivers. SEMICON Japan will enable attendees to explore key technologies and business models necessary to grow in the coming years. On December 3, SEMICON Japan opens at 9:30am with a full day of speakers including:
Accenture Japan Ltd — Chikatomo Hodo, president and country managing director.
IBM Japan — Chieko Asakawa, IBM fellow.
Scripps Translational Science Institute — Donald Jones, chief digital officer.
Toyota — Tokuhisa Nomura, executive general manager.
Intel Japan — Makiko Eda, GM and president of Intel Japan.
ARM K.K. — Yuzuru Utsumi, president.
Toshiba — Yasuo Naruke, executive officer, corporate EVP and CEO, semiconductor & storage.
National Institute of Information and Communication Technology (NIICT) — Miwako Doi, auditor.
SEMICON Japan will also highlight emerging opportunities in its workforce composition. In Japan, 14.7 percent of the students in science and engineering departments are women (source: Japan Ministry of Education, Culture, Sports, Science and Technology). SEMI will host a forum on “Women in Business” in Tokyo for the first time to discuss the gender diversity strategy, featuring women executives.
SEMICON Japan 2014, the largest exhibition in Japan for semiconductor manufacturing and related processing technology, will take place at its new venue in Tokyo Big Sight in Tokyo on December 3-5.
A deep program spans from the 33rd annual SEMI Technology Symposium (STS) which begins on December 3, includes sessions on power devices, DFM, lithography, MEMS, packaging, and more to the new World of IoT (Internet of Things).
While the semiconductor and IC manufacturing industries have undergone consolidation, a surge in new investment points to a rebound in related spending in Japan. The semiconductor equipment market in Japan is forecast to grow both in 2014 and 2015.
Drivers for the increased investment are: memory devices, power semiconductors and “More than Moore” semiconductor technologies. According to the SEMI World Fab Forecast, in 2014, Japan will spend more than $10 billion in 2014 on semiconductor equipment and materials. The projection for 2015 is to more than double semiconductor equipment spending to $4.2 billion.
SEMICON Japan 2014 will bring Japan’s rebounding semiconductor equipment market into focus and the underlying technology and business drivers. SEMICON Japan will enable attendees to explore key technologies and business models necessary to grow in the coming years. On December 3, SEMICON Japan opens at 9:30am with a full day of speakers including:
Accenture Japan Ltd — Chikatomo Hodo, president and country managing director.
IBM Japan — Chieko Asakawa, IBM fellow.
Scripps Translational Science Institute — Donald Jones, chief digital officer.
Toyota — Tokuhisa Nomura, executive general manager.
Intel Japan — Makiko Eda, GM and president of Intel Japan.
ARM K.K. — Yuzuru Utsumi, president.
Toshiba — Yasuo Naruke, executive officer, corporate EVP and CEO, semiconductor & storage.
National Institute of Information and Communication Technology (NIICT) — Miwako Doi, auditor.
SEMICON Japan will also highlight emerging opportunities in its workforce composition. In Japan, 14.7 percent of the students in science and engineering departments are women (source: Japan Ministry of Education, Culture, Sports, Science and Technology). SEMI will host a forum on “Women in Business” in Tokyo for the first time to discuss the gender diversity strategy, featuring women executives.
Semiconductor manufacturing: Present at ASMC 2015
SAN JOSE, USA: SEMI announced that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 10.
ASMC, which takes place May 3-6, 2015 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials.
ASMC, in its 26th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.
Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are now due November 10, 2014.
This year, SEMI is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:
* 3D/TSV/Interposer
* Advanced Metrology
* Advanced Equipment Processes and Materials
* Advanced Patterning / Design for Manufacturability
* Advanced Process Control (APC)
* Contamination Free Manufacturing (CFM)
* Data Management and Data Mining Tools
* Defect Inspection and Reduction
* Discrete Power Devices
* Enabling Technologies and Innovative Devices
* Equipment Reliability and Productivity Enhancements
* Fabless Experience
* Factory Automation
* Green Factory
* Industrial Engineering
* Lean Manufacturing
* Yield Enhancement
* Yield Methodologies.
ASMC, which takes place May 3-6, 2015 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials.
ASMC, in its 26th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.
Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are now due November 10, 2014.
This year, SEMI is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:
* 3D/TSV/Interposer
* Advanced Metrology
* Advanced Equipment Processes and Materials
* Advanced Patterning / Design for Manufacturability
* Advanced Process Control (APC)
* Contamination Free Manufacturing (CFM)
* Data Management and Data Mining Tools
* Defect Inspection and Reduction
* Discrete Power Devices
* Enabling Technologies and Innovative Devices
* Equipment Reliability and Productivity Enhancements
* Fabless Experience
* Factory Automation
* Green Factory
* Industrial Engineering
* Lean Manufacturing
* Yield Enhancement
* Yield Methodologies.
Wednesday, October 29, 2014
Apple iPad Air 2 largely holds line on features and costs
EL SEGUNDO, USA: With a design and feature set only incrementally different from the original iPad Air, the new iPad Air 2 carries a nearly identical hardware cost as its predecessor, according to the Teardown Analysis Service at IHS Inc.
The 16-gigabyte (GB) Wi-Fi-only version of the Apple iPad Air 2 sports a bill of materials (BOM) of $270, based on a preliminary estimate. When the $5 manufacturing cost is added, the cost rises to $275.
This compares to the $269 BOM for the 16GB version of the original Apple iPad Air, based on a finalized estimate from IHS in November 2013.
Although the profit margin appears to be the same for Apple at the low end of the iPad Air 2 line, the product produces lower gross margins for Apple at the high end with 64GB and 128GB worth of NAND flash. This is because the 64GB and 128GB models of iPad Air 2 are selling at the same price point as the original iPad Air 32GB and 64GB models. The additional cost of memory trims the estimated margins slightly.
“The Air 2 delivers a series of refinements compared to the original Air but features nothing earthshaking,” said Andrew Rassweiler, senior director, cost benchmarking services for IHS.
“With largely identical display specifications and minor improvements in most other areas, Apple continues to offer evolutionary upgrades to the iPad lineup. It’s interesting to note that by offering the consumer a 128GB model for the same price as last year’s 64GB iPad Air, Apple actually has taken down our estimated margins a bit on both the 64GB and 128GB models. The increased memory configurations to 64GB and 128GB are some of the key upgrades here.”
The 16-gigabyte (GB) Wi-Fi-only version of the Apple iPad Air 2 sports a bill of materials (BOM) of $270, based on a preliminary estimate. When the $5 manufacturing cost is added, the cost rises to $275.
This compares to the $269 BOM for the 16GB version of the original Apple iPad Air, based on a finalized estimate from IHS in November 2013.
Although the profit margin appears to be the same for Apple at the low end of the iPad Air 2 line, the product produces lower gross margins for Apple at the high end with 64GB and 128GB worth of NAND flash. This is because the 64GB and 128GB models of iPad Air 2 are selling at the same price point as the original iPad Air 32GB and 64GB models. The additional cost of memory trims the estimated margins slightly.
“The Air 2 delivers a series of refinements compared to the original Air but features nothing earthshaking,” said Andrew Rassweiler, senior director, cost benchmarking services for IHS.
“With largely identical display specifications and minor improvements in most other areas, Apple continues to offer evolutionary upgrades to the iPad lineup. It’s interesting to note that by offering the consumer a 128GB model for the same price as last year’s 64GB iPad Air, Apple actually has taken down our estimated margins a bit on both the 64GB and 128GB models. The increased memory configurations to 64GB and 128GB are some of the key upgrades here.”
SiTime to be acquired by MegaChips for $200 million
SUNNYVALE, USA: SiTime Corp., a MEMS and analog semiconductor company, announced that it has signed a definitive agreement under which MegaChips Corp., a top 25 fabless semiconductor company based in Japan, will acquire SiTime for $200 million in cash.
This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.
“SiTime’s founders, Markus Lutz and Dr. Aaron Partridge, started the company with a vision of developing game-changing MEMS and analog technology to revolutionize the $5 billion timing industry,” said Rajesh Vashist, CEO of SiTime.
“Through innovation, passion and focus, we’ve successfully delivered on this vision. Today, SiTime is the overwhelming leader – we have 1000 customers, 250 million units shipped, major design wins in all electronics segments, and a roadmap that extends SiTime’s MEMS technology to all timing markets.”
“Every SiTime employee is excited to be part of MegaChips as we share a common entrepreneurial culture,” continued Vashist. “MegaChips’ financial strength and scale, with SiTime’s innovation and passion, will rapidly accelerate the adoption of MEMS timing solutions.”
While the world of electronics has delivered many innovations, the clock function, which is the heartbeat in all electronics, still uses 75-year-old quartz technology. SiTime’s innovative MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.
This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.
“SiTime’s founders, Markus Lutz and Dr. Aaron Partridge, started the company with a vision of developing game-changing MEMS and analog technology to revolutionize the $5 billion timing industry,” said Rajesh Vashist, CEO of SiTime.
“Through innovation, passion and focus, we’ve successfully delivered on this vision. Today, SiTime is the overwhelming leader – we have 1000 customers, 250 million units shipped, major design wins in all electronics segments, and a roadmap that extends SiTime’s MEMS technology to all timing markets.”
“Every SiTime employee is excited to be part of MegaChips as we share a common entrepreneurial culture,” continued Vashist. “MegaChips’ financial strength and scale, with SiTime’s innovation and passion, will rapidly accelerate the adoption of MEMS timing solutions.”
While the world of electronics has delivered many innovations, the clock function, which is the heartbeat in all electronics, still uses 75-year-old quartz technology. SiTime’s innovative MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.
Tuesday, October 28, 2014
Mentor Graphics announces Xpedition system designer for comprehensive multi-board systems development
WILSONVILLE, USA: Mentor Graphics Corp. announced its newest offering and key building block in the Xpedition® platform, the Xpedition Systems Designer product for multi-board systems connectivity.
The Xpedition Systems Designer product captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronization processes to ensure team collaboration with accuracy and faster design productivity.
Current systems design processes for advanced electronics are fraught with multiple, disconnected tools used for system definition, with no standard methodology to synchronize and transfer design data between design disciplines and abstraction levels. This results in incorrect electrical connections, mechanical interference, and the high costs of manual synchronization.
The Xpedition Systems Designer product resolves this problem as the industry's only single, integrated, and automated methodology that captures complete logic system definitions. The system may consist of multiple boards, cables and other system elements, such as backplane, cable assemblies, sensors and actuators. This solution enables consistency and completeness of the multi-board system description.
"Systems design involves collaboration across disciplines, and is critical to modern product development. Traditional design practices isolate systems capture from the rest of the process, lowering team productivity, stifling innovation, and increasing product cost," stated John MacKrell, VP, Systems Engineering Knowledge Council lead of CIMdata. "Mentor Graphics' new systems design technology enables engineering teams to capture system designs, while collaborating effectively with all those involved in the design and implementation process to optimize the end product."
The Xpedition Systems Designer product replaces time- and resource-consuming manual processes and the redundant re-entry of data with automatic synchronization of design changes across multiple levels and disciplines.
This unique design "cockpit" enables system-wide partitioning of logical system blocks into individual PCBs. The environment fully supports concurrent design, enabling team members to simultaneously engineer and collaborate on different components of the system.
"Our new Xpedition platform delivers 'industry-first' technologies and our new Systems Designer product is a clear example," stated Henry Potts, VP and GM of Mentor Graphics Systems Design Division. "Xpedition Systems Designer was developed as the industry's best environment for design connectivity and team collaboration to deliver consistency of design integrity across disparate domains, tools and individuals."
The Xpedition Systems Designer product captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronization processes to ensure team collaboration with accuracy and faster design productivity.
Current systems design processes for advanced electronics are fraught with multiple, disconnected tools used for system definition, with no standard methodology to synchronize and transfer design data between design disciplines and abstraction levels. This results in incorrect electrical connections, mechanical interference, and the high costs of manual synchronization.
The Xpedition Systems Designer product resolves this problem as the industry's only single, integrated, and automated methodology that captures complete logic system definitions. The system may consist of multiple boards, cables and other system elements, such as backplane, cable assemblies, sensors and actuators. This solution enables consistency and completeness of the multi-board system description.
"Systems design involves collaboration across disciplines, and is critical to modern product development. Traditional design practices isolate systems capture from the rest of the process, lowering team productivity, stifling innovation, and increasing product cost," stated John MacKrell, VP, Systems Engineering Knowledge Council lead of CIMdata. "Mentor Graphics' new systems design technology enables engineering teams to capture system designs, while collaborating effectively with all those involved in the design and implementation process to optimize the end product."
The Xpedition Systems Designer product replaces time- and resource-consuming manual processes and the redundant re-entry of data with automatic synchronization of design changes across multiple levels and disciplines.
This unique design "cockpit" enables system-wide partitioning of logical system blocks into individual PCBs. The environment fully supports concurrent design, enabling team members to simultaneously engineer and collaborate on different components of the system.
"Our new Xpedition platform delivers 'industry-first' technologies and our new Systems Designer product is a clear example," stated Henry Potts, VP and GM of Mentor Graphics Systems Design Division. "Xpedition Systems Designer was developed as the industry's best environment for design connectivity and team collaboration to deliver consistency of design integrity across disparate domains, tools and individuals."
Synopsys' USB 3.1 IP solution enables 10 Gbps data transfer speeds
MOUNTAIN VIEW, USA: Synopsys Inc. has introduced the industry's first USB 3.1 IP solution, consisting of DesignWare USB 3.1 Device Controller, an IP Virtual Development Kit (VDK) and verification IP (VIP) to accelerate the development of high-performance storage, digital office and mobile system-on-chip (SoC) applications.
Synopsys' DesignWare USB 3.1 IP solutions support 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.
"Mobile, storage and digital office applications that will take advantage of USB 3.1's 10 Gbps performance are in development now," said Terry Moore, CEO at MCCI. "Designers facing tight schedules can save up to twenty months of engineering effort by using their existing DesignWare USB 3.0 software or, if changing controllers or operating systems, by using MCCI's pre-tested off-the-shelf Datapump USB device stack."
"As an active member of the USB-IF for more than 18 years, Synopsys continues to develop IP products that ease the integration and adoption of the latest USB specifications," said Jeff Ravencraft, USB-IF president and COO. "Initial USB 3.1 products are expected to appear in early 2015 and the availability of integration-ready USB 3.1 IP is critical. Companies like Synopsys give designers the ability to more easily incorporate the USB 3.1 interface into their SoCs, pushing USB performance ever higher."
The DesignWare USB 3.1 IP VDK, part of the Synopsys IP Accelerated initiative, helps developers quickly bring-up, enhance and optimize existing software for their specific DesignWare USB 3.1 Device Controller configuration.
The IP VDK consists of a reference virtual prototype that includes a processor subsystem reference design, a configurable model of the DesignWare USB 3.1 Controller IP, a Linux software stack and reference drivers.
Software developers can use the IP VDK as a proven target for early software development, bring-up, debug and test in parallel with SoC development. Hardware developers can use the HAPS® FPGA-based prototyping system for hardware/software integration and system validation of USB 3.1 designs, as demonstrated in November 2013.
Synopsys' USB 3.1 VIP is based on Synopsys' native SystemVerilog and native UVM architecture, offering ease of integration, high performance, configurability, coverage and debug to speed the protocol verification process.
The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
"As a leading provider of USB IP for more than a decade, Synopsys provides the high-quality IP designers need to meet their evolving power, performance and area requirements," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With our extensive knowledge in developing USB IP, more than 3,000 USB design wins and billions of SoCs shipped with DesignWare USB IP, designers know they can rely on Synopsys when integrating the latest USB functionality into their SoCs."
Synopsys' DesignWare USB 3.1 IP solutions support 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.
"Mobile, storage and digital office applications that will take advantage of USB 3.1's 10 Gbps performance are in development now," said Terry Moore, CEO at MCCI. "Designers facing tight schedules can save up to twenty months of engineering effort by using their existing DesignWare USB 3.0 software or, if changing controllers or operating systems, by using MCCI's pre-tested off-the-shelf Datapump USB device stack."
"As an active member of the USB-IF for more than 18 years, Synopsys continues to develop IP products that ease the integration and adoption of the latest USB specifications," said Jeff Ravencraft, USB-IF president and COO. "Initial USB 3.1 products are expected to appear in early 2015 and the availability of integration-ready USB 3.1 IP is critical. Companies like Synopsys give designers the ability to more easily incorporate the USB 3.1 interface into their SoCs, pushing USB performance ever higher."
The DesignWare USB 3.1 IP VDK, part of the Synopsys IP Accelerated initiative, helps developers quickly bring-up, enhance and optimize existing software for their specific DesignWare USB 3.1 Device Controller configuration.
The IP VDK consists of a reference virtual prototype that includes a processor subsystem reference design, a configurable model of the DesignWare USB 3.1 Controller IP, a Linux software stack and reference drivers.
Software developers can use the IP VDK as a proven target for early software development, bring-up, debug and test in parallel with SoC development. Hardware developers can use the HAPS® FPGA-based prototyping system for hardware/software integration and system validation of USB 3.1 designs, as demonstrated in November 2013.
Synopsys' USB 3.1 VIP is based on Synopsys' native SystemVerilog and native UVM architecture, offering ease of integration, high performance, configurability, coverage and debug to speed the protocol verification process.
The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
"As a leading provider of USB IP for more than a decade, Synopsys provides the high-quality IP designers need to meet their evolving power, performance and area requirements," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With our extensive knowledge in developing USB IP, more than 3,000 USB design wins and billions of SoCs shipped with DesignWare USB IP, designers know they can rely on Synopsys when integrating the latest USB functionality into their SoCs."
Synopsys IC Compiler II delivers five-fold implementation speed up
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its IC Complier II place-and-route tool enabled Panasonic Corporation System LSI Business Division (Panasonic SoC) to achieve silicon success with their high-end multimedia chip.
Unveiled at Synopsys User Group (SNUG) in Silicon Valley earlier this year, IC Compiler II is a game-changing successor to the IC Compiler product, the industry's current leading place-and-route solution for advanced designs at both established and emerging nodes.
Key capabilities in IC Compiler II include rapid design exploration, unique new clock-building, analytics-driven optimization to boost quality-of-results and extensive use of multi-mode and multi-corner optimization throughout the flow to accelerate turnaround time. The unique benefits it offered with five times faster implementation, IC Compiler II is now seeing expanded use to other designs at 40 nanometer (nm) and 28 nm process technology nodes.
"IC Compiler II was instrumental in enabling us to hit our market window and achieve silicon success for our complex multimedia chip. We are now entering volume production," said Hiroki Tomoshige, GM at Panasonic Corp. System LSI Business Division, Division 3, Second Development Group. "We are very pleased with the breakthrough performance IC Compiler II has delivered to shorten our design cycles and get our competitive products to market faster."
IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity. Based on a new multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II delivers a groundbreaking 10-times increase in design throughput.
IC Complier II's "analytically-global" optimization provides faster, broader and more convergent physical synthesis and closure. This natively multi-threaded technique utilizes new, highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimization. Early and broad analysis enables optimization for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum.
Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.
"The unique benefits it offers with five times faster implementation illustrates why our customers are seeing IC Compiler II as a game-changing solution that is redefining the implementation landscape," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "We are engaged broadly to bring the power of 10X delivered by IC Compiler II to more customers and help them get more competitive products to market faster."
Unveiled at Synopsys User Group (SNUG) in Silicon Valley earlier this year, IC Compiler II is a game-changing successor to the IC Compiler product, the industry's current leading place-and-route solution for advanced designs at both established and emerging nodes.
Key capabilities in IC Compiler II include rapid design exploration, unique new clock-building, analytics-driven optimization to boost quality-of-results and extensive use of multi-mode and multi-corner optimization throughout the flow to accelerate turnaround time. The unique benefits it offered with five times faster implementation, IC Compiler II is now seeing expanded use to other designs at 40 nanometer (nm) and 28 nm process technology nodes.
"IC Compiler II was instrumental in enabling us to hit our market window and achieve silicon success for our complex multimedia chip. We are now entering volume production," said Hiroki Tomoshige, GM at Panasonic Corp. System LSI Business Division, Division 3, Second Development Group. "We are very pleased with the breakthrough performance IC Compiler II has delivered to shorten our design cycles and get our competitive products to market faster."
IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity. Based on a new multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II delivers a groundbreaking 10-times increase in design throughput.
IC Complier II's "analytically-global" optimization provides faster, broader and more convergent physical synthesis and closure. This natively multi-threaded technique utilizes new, highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimization. Early and broad analysis enables optimization for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum.
Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.
"The unique benefits it offers with five times faster implementation illustrates why our customers are seeing IC Compiler II as a game-changing solution that is redefining the implementation landscape," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "We are engaged broadly to bring the power of 10X delivered by IC Compiler II to more customers and help them get more competitive products to market faster."
Micron, Wave Systems, Lenovo and American Megatrends to create new industry standard to meet global security requirements
BOISE, USA: Micron Technology Inc.and Wave Systems Corp. intend to expand their collaboration to include Lenovo and American Megatrends Inc.(AMI).
The four companies plan to develop advanced enterprise-class security offerings to address the escalating concerns of governments and multinational businesses.
To meet the overall objective of verifying and securing software components, these solutions will significantly strengthen the Core Root of Trust for Measurement (CRTM) to offer best-in-class protection against current and emerging pre-boot threats within the supply chain. The companies intend for these solutions to form the basis of a new industry standard designed to ensure the integrity of the supply chain.
According to the 2014 Verizon DBIR report, supply chain vulnerabilities and third-party vendors are still a leading cause of enterprise data breaches (Source, Verizon DBIR, 2014). With major brands continually leaking sensitive enterprise data, it is becoming even more critical to architect a comprehensive enterprise security suite that protects memory content from its inception in manufacturing throughout a computing device's life cycle.
By providing verification of the CRTM, the first BIOS code that executes, the security of system measurements can be ensured rather than implicitly trusted, reducing the risk of supply chain attacks. A centrally managed security solution working in conjunction with a client's core root of trust for measurement provides client system integrity throughout the supply chain.
A combined security solution from Micron, Wave, Lenovo and AMI would address the foundational level of a client's security by enabling advanced protection, detection and recovery capabilities for memory content, creating an unrivaled level of trust from the supply chain to the corporate environment. The planned software solution will integrate with the Trusted Platform Module and other hardware components to provide notification, remote management, and further remediation options for the enterprise.
The four companies plan to develop advanced enterprise-class security offerings to address the escalating concerns of governments and multinational businesses.
To meet the overall objective of verifying and securing software components, these solutions will significantly strengthen the Core Root of Trust for Measurement (CRTM) to offer best-in-class protection against current and emerging pre-boot threats within the supply chain. The companies intend for these solutions to form the basis of a new industry standard designed to ensure the integrity of the supply chain.
According to the 2014 Verizon DBIR report, supply chain vulnerabilities and third-party vendors are still a leading cause of enterprise data breaches (Source, Verizon DBIR, 2014). With major brands continually leaking sensitive enterprise data, it is becoming even more critical to architect a comprehensive enterprise security suite that protects memory content from its inception in manufacturing throughout a computing device's life cycle.
By providing verification of the CRTM, the first BIOS code that executes, the security of system measurements can be ensured rather than implicitly trusted, reducing the risk of supply chain attacks. A centrally managed security solution working in conjunction with a client's core root of trust for measurement provides client system integrity throughout the supply chain.
A combined security solution from Micron, Wave, Lenovo and AMI would address the foundational level of a client's security by enabling advanced protection, detection and recovery capabilities for memory content, creating an unrivaled level of trust from the supply chain to the corporate environment. The planned software solution will integrate with the Trusted Platform Module and other hardware components to provide notification, remote management, and further remediation options for the enterprise.
eInfochips demos medical imaging, video processing and mechanical engineering solutions for medical devices
AHMEDABAD, INDIA: eInfochips, a leading engineering R&D services company, will be at MedTech World’s popular MD&M event in Minneapolis to demonstrate its software, mechanical and hardware engineering services available for design of IEC 60601, IEC 62304 and ISO14971 compliant medical devices.
The company will highlight its track record of improving time-to-market for Fortune 500 clients on medical imaging, diagnostics, tele-medicine, wearable medical devices, and surgical equipment.
Parag Mehta, chief marketing and business development officer at eInfochips, said: “We see a transformation in the industry, with products becoming power-efficient, performance-driven that come with ultra-small form factors. We are leading this transition with our design, test and re-engineering services for Fortune 500 companies.”
The company will showcase its expertise at MD&M Minneapolis Conference at Booth #1052, on 29th & 30th Oct 2014
The company will highlight its track record of improving time-to-market for Fortune 500 clients on medical imaging, diagnostics, tele-medicine, wearable medical devices, and surgical equipment.
Parag Mehta, chief marketing and business development officer at eInfochips, said: “We see a transformation in the industry, with products becoming power-efficient, performance-driven that come with ultra-small form factors. We are leading this transition with our design, test and re-engineering services for Fortune 500 companies.”
The company will showcase its expertise at MD&M Minneapolis Conference at Booth #1052, on 29th & 30th Oct 2014
Symtavision and Renesas collaborate on joint timing analysis methodology for multicore MCUs
BRAUNSCHWEIG, GERMANY: Closely collaborating with Renesas Electronics, Symtavision, the global leader in timing analysis solutions for planning, optimizing and verifying embedded real-time systems, has developed an integrated, model- and trace-based methodology for the Renesas RH850 family of multicore MCUs as well as other Renesas target MCU architectures.
Central to the Symtavision/Renesas integrated methodology for multicore ECUs are Symtavision’s SymTA/S tool suite for model-based timing analysis, optimization and synthesis, combined with Symtavision’s powerful TraceAnalyzer solution for visualizing and analyzing timing from measurements and simulations.
Both SymTA/S and TraceAnalyzer are used extensively in the automotive industry for developing efficient, safe and reliable ECUs, networks and distributed systems.
The methodology involves target tracing to gather fundamental timing data in a realistic environment on the target platform (or one that is predictably related). A range of established tracing tools such as those from Green Hills Software, Gliwa, iSYSTEM or Lauterbach can be used for this purpose.
Symtavision’s TraceAnalyzer then processes this data to visualize and validate the internal scheduling of the device and derive key metrics such as memory access times, runnable execution times and patterns of sporadic interrupts. This allows the simple creation of dedicated RH850 virtual performance models in SymTA/S.
These models facilitate an early assessment of design alternatives to ensure that all software can execute in real-time and also provide a basis for the continuous validation of model assumptions versus actual implementation.
Furthermore, the dedicated RH850 models ensure that key multicore-related design challenges such as optimal software and task partitioning, as well as data allocation and arbitration, are systematically addressed. The models can be extended seamlessly to analysis of distributed functions over CAN, Ethernet, FlexRay or LIN.
Central to the Symtavision/Renesas integrated methodology for multicore ECUs are Symtavision’s SymTA/S tool suite for model-based timing analysis, optimization and synthesis, combined with Symtavision’s powerful TraceAnalyzer solution for visualizing and analyzing timing from measurements and simulations.
Both SymTA/S and TraceAnalyzer are used extensively in the automotive industry for developing efficient, safe and reliable ECUs, networks and distributed systems.
The methodology involves target tracing to gather fundamental timing data in a realistic environment on the target platform (or one that is predictably related). A range of established tracing tools such as those from Green Hills Software, Gliwa, iSYSTEM or Lauterbach can be used for this purpose.
Symtavision’s TraceAnalyzer then processes this data to visualize and validate the internal scheduling of the device and derive key metrics such as memory access times, runnable execution times and patterns of sporadic interrupts. This allows the simple creation of dedicated RH850 virtual performance models in SymTA/S.
These models facilitate an early assessment of design alternatives to ensure that all software can execute in real-time and also provide a basis for the continuous validation of model assumptions versus actual implementation.
Furthermore, the dedicated RH850 models ensure that key multicore-related design challenges such as optimal software and task partitioning, as well as data allocation and arbitration, are systematically addressed. The models can be extended seamlessly to analysis of distributed functions over CAN, Ethernet, FlexRay or LIN.
Automotive bus technology delivers superior digital audio quality
USA: Analog Devices Inc. has introduced a digital audio bus technology capable of distributing audio and control data together with clock and power over a single, unshielded twisted-pair wire.
The AD2410 transceiver is the first in a family of devices that enables ADI’s new Automotive Audio Bus (A²B), which significantly reduces the weight of existing cable harnesses, resulting in improved vehicle fuel efficiency while delivering high fidelity audio. The AD2410 transceiver also eliminates the need for expensive microcontrollers with large memories that are required in existing digital bus architectures.
“As an early implementer of ADI’s A²B, Panasonic Automotive found the technology to significantly reduce cabling complexity and associated cost and weight of next-generation infotainment systems, key areas of focus for Panasonic’s OEM customers,” said Jonathan Lane, Group manager, Audio & Acoustics, part of Panasonic Automotive Systems Co. of America (PASA) Advanced Development Engineering.
“We believe A²B to be well suited to address applications such as microphone arrays and Active Noise Cancellation, a leading area of expertise for Panasonic that we expect to be an integral component of next-generation infotainment systems.”
The AD2410 transceiver is the first in a family of devices that enables ADI’s new Automotive Audio Bus (A²B), which significantly reduces the weight of existing cable harnesses, resulting in improved vehicle fuel efficiency while delivering high fidelity audio. The AD2410 transceiver also eliminates the need for expensive microcontrollers with large memories that are required in existing digital bus architectures.
“As an early implementer of ADI’s A²B, Panasonic Automotive found the technology to significantly reduce cabling complexity and associated cost and weight of next-generation infotainment systems, key areas of focus for Panasonic’s OEM customers,” said Jonathan Lane, Group manager, Audio & Acoustics, part of Panasonic Automotive Systems Co. of America (PASA) Advanced Development Engineering.
“We believe A²B to be well suited to address applications such as microphone arrays and Active Noise Cancellation, a leading area of expertise for Panasonic that we expect to be an integral component of next-generation infotainment systems.”
Cadence announces Virtuoso Liberate AMS
SAN JOSE, USA: Cadence Design Systems Inc. announced the Cadence Virtuoso Liberate AMS characterization solution, the industry's first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os.
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Monday, October 27, 2014
Cadence announces industry's first 25G Ethernet verification IP
SAN JOSE, USA: Cadence Design Systems Inc. announced the industry's first Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification.
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
SMIC and ASML sign volume purchase agreement worth 450 million Euros
SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. and ASML Holding N.V. announced the signing of a volume purchase agreement (VPA) that will provide SMIC with lithography systems from ASML.
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
SK Hynix accelerates memory development with Synopsys Verdi
MOUNTAIN VIEW, USA: Synopsys Inc. announced that SK Hynix Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys and Gowin Semiconductor ink multi-year OEM agreement for FPGA design software
MOUNTAIN VIEW, USA: Synopsys Inc. has announced a multi-year OEM agreement with Gowin Semiconductor for Synopsys Synplify Pro FPGA synthesis tools.
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
AMD Radeon supercharges Sid Meier’s Civilization: Beyond Earth with Mantle Graphics API
USA: AMD joins Firaxis Games in celebrating the release of Sid Meier’s Civilization: Beyond Earth, which features day-one support for AMD’s Mantle graphics API to enable top gaming performance for AMD Radeon graphics customers.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
Mentor Graphics to host User2User 2014 India conference in Bangalore
BANGALORE, INDIA: Mentor Graphics Corp. announced that it will host its 10th annual User2User India conference on October 31, 2014 at Vivanta by Taj (the former Taj Residency), M.G.Road, Trinity Circle, Bangalore.
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
Worldwide semiconductor market is forecasted to be $325 billion in 2014, up 6.5 percent from 2013
USA: The World Semiconductor Trade Statistics (WSTS) has released its updated semiconductor market forecast. WSTS predicts that the world semiconductor market will reach $325 billion in 2014, up 6.5 percent from 2013.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions except Japan will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions except Japan will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
Friday, October 24, 2014
Lucintel estimates that Asia Pacific will consume more than 35 percent of bulk molding compounds market by 2019
IRVING, USA: Bulk molding compounds (BMC) are used in a variety of markets, such as transportation, electrical & electronics, and consumer goods.
Bulk molding compounds have excellent flow characteristics, dielectric properties, and flame resistance which make them well-suited to a wide variety of applications, requiring precision in detail and dimensions as well as high performance.
Bulk molding compounds are ideal for headlamps, circuit breakers, housings, and valve covers due to their lightweight and higher thermal resistance properties. The Asia Pacific region is expected to represent more than 35 percent of the global bulk molding compounds market by 2019.
Bulk molding compounds (BMC) are expected to grow at a CAGR of 6.8 percent during 2014-2019. Electrical & electronics will remain the largest end user industry. Citadel Plastics, IDI Composites, Polynt, Premix, and Showa Denko are some of the suppliers of BMC materials for various applications. These companies are the important players in the BMC materials market because of their innovation and investment in research and development to find new applications.
Bulk molding compounds have excellent flow characteristics, dielectric properties, and flame resistance which make them well-suited to a wide variety of applications, requiring precision in detail and dimensions as well as high performance.
Bulk molding compounds are ideal for headlamps, circuit breakers, housings, and valve covers due to their lightweight and higher thermal resistance properties. The Asia Pacific region is expected to represent more than 35 percent of the global bulk molding compounds market by 2019.
Bulk molding compounds (BMC) are expected to grow at a CAGR of 6.8 percent during 2014-2019. Electrical & electronics will remain the largest end user industry. Citadel Plastics, IDI Composites, Polynt, Premix, and Showa Denko are some of the suppliers of BMC materials for various applications. These companies are the important players in the BMC materials market because of their innovation and investment in research and development to find new applications.
Thursday, October 23, 2014
Apple and Samsung drive adoption of next-generation sensors
EL SEGUNDO, USA: Propelled by the race between Apple and Samsung to enhance their mobile products with cutting-edge sensor technology, the market for sensors in cellphones and tablets is set to nearly triple from 2012 through 2018, according to IHS Technology.
Worldwide market revenue for sensors used in mobile handsets and media tablets will rise to $6.5 billion in 2018, up from $2.3 billion in 2012. The fastest-expanding portion of the mobile sensor segment will be emerging devices, whose revenue will surge to $2.3 billion in 2018, up from just $24 million in 2012. In 2013, this segment posted dramatic growth, with revenue rising to more than $500 million.
“The next wave of sensor technology in smartphones and tablets has arrived,” said Marwan Boustany, IHS senior analyst for microelectromechanical systems (MEMS) and sensors.
“Led by Apple and Samsung, the mobile market is moving beyond simply integrating established devices like motion sensors and now is including next-generation features like fingerprint and environment/health sensors. Adoption of these newer devices will drive the expansion of the mobile sensor device market in the coming years.”
Established sensors in mobile devices include motion sensors, light sensors and MEMS microphones. Emerging sensors consist of new devices including fingerprint, optical pulse, humidity, gas, ultraviolet (UV) and thermal imaging.
Information in this media release is contained in the new IHS Technology report entitled Emerging Sensors in Handsets & Tablets Report – 2014 from the Semiconductors & Components service.
Heightened sensors
Apple initiated the market for fingerprint sensors in mobile devices with the release of the iPhone 5s in 2013.
“Fingerprint sensors have arrived in force. IHS forecasts that shipments of fingerprint-enabled devices will reach 1.4 billion units in 2020,” Boustany said. “This is more than four times the 317 million units expected to be shipped by the end of 2014.”
The fingerprint sensor market is beginning to gain traction at other companies outside of Apple. New devices with fingerprint sensors include Samsung’s flagship model—the Galaxy S5—and Huawei’s top-of-the-line smartphone, the Ascend Mate 7, both of which began shipping in 2014.
For its part, Samsung has pioneered the deployment of other devices, including environmental and health sensors in the flagship models introduced by the company during the last 18 months. Samsung rolled out a humidity sensor in the Galaxy S4, a pulse sensor in the Galaxy S5 and a UV sensor in the Note 4.
Asian sensation
Fingerprint sensors play a key role in mobile payment services, providing authentication for systems like Apple Pay. Other banks and financial institutions, including Visa, MasterCard and PayPal are also working to support mobile payments and biometric authentication.
“This fingerprint market has all its requirements for success converging at the right time,” Boustany said.
Mobile payment services are expected to gain popularity not just in Europe and North America, but also in Asia.
With the increasing demand for sensor technology in Asia, IHS expects Chinese smartphone original equipment manufacturers (OEM) to be the next driver for a new generation of sensors.
Humidity sensors have been used in Chinese handsets since 2011. In the future, air-quality sensors will experience growing usage in China.
The first gas sensors have just been designed in by Chinese smartphone OEMs. IHS expects these phones will enter the market during the first half of 2015. There is also a specific demand for sensors that can detect particle pollution in large Chinese cities such as Beijing or Shanghai.
Extrasensory perception
In terms of revenue, fingerprint sensors now dominate the mobile market, followed by optical pulse sensors, humidity and UV sensors. IHS anticipates gas sensors will join the fray in 2015 and thermal imagers will arrive during the 2018 time period.
Thermal imagers using microbolometer sensors emerged from the technology of forward-looking infrared (FLIR) systems in 2014 as accessories for the iPhone 5s. However, it will take a few more years before these sensors decline enough in pricing to be embedded in smartphones.
IHS predicts that Samsung will adopt gas/chemical sensors in the Note 6 that will be introduced in 2016. This is because gas/chemical sensor technology will have matured and use cases will be more clearly defined by then.
Some sensors that have appeared in smartphones are likely to migrate to wearables, which in some cases are better platforms for health or environmental sensors.
Worldwide market revenue for sensors used in mobile handsets and media tablets will rise to $6.5 billion in 2018, up from $2.3 billion in 2012. The fastest-expanding portion of the mobile sensor segment will be emerging devices, whose revenue will surge to $2.3 billion in 2018, up from just $24 million in 2012. In 2013, this segment posted dramatic growth, with revenue rising to more than $500 million.
“The next wave of sensor technology in smartphones and tablets has arrived,” said Marwan Boustany, IHS senior analyst for microelectromechanical systems (MEMS) and sensors.
“Led by Apple and Samsung, the mobile market is moving beyond simply integrating established devices like motion sensors and now is including next-generation features like fingerprint and environment/health sensors. Adoption of these newer devices will drive the expansion of the mobile sensor device market in the coming years.”
Established sensors in mobile devices include motion sensors, light sensors and MEMS microphones. Emerging sensors consist of new devices including fingerprint, optical pulse, humidity, gas, ultraviolet (UV) and thermal imaging.
Information in this media release is contained in the new IHS Technology report entitled Emerging Sensors in Handsets & Tablets Report – 2014 from the Semiconductors & Components service.
Heightened sensors
Apple initiated the market for fingerprint sensors in mobile devices with the release of the iPhone 5s in 2013.
“Fingerprint sensors have arrived in force. IHS forecasts that shipments of fingerprint-enabled devices will reach 1.4 billion units in 2020,” Boustany said. “This is more than four times the 317 million units expected to be shipped by the end of 2014.”
The fingerprint sensor market is beginning to gain traction at other companies outside of Apple. New devices with fingerprint sensors include Samsung’s flagship model—the Galaxy S5—and Huawei’s top-of-the-line smartphone, the Ascend Mate 7, both of which began shipping in 2014.
For its part, Samsung has pioneered the deployment of other devices, including environmental and health sensors in the flagship models introduced by the company during the last 18 months. Samsung rolled out a humidity sensor in the Galaxy S4, a pulse sensor in the Galaxy S5 and a UV sensor in the Note 4.
Asian sensation
Fingerprint sensors play a key role in mobile payment services, providing authentication for systems like Apple Pay. Other banks and financial institutions, including Visa, MasterCard and PayPal are also working to support mobile payments and biometric authentication.
“This fingerprint market has all its requirements for success converging at the right time,” Boustany said.
Mobile payment services are expected to gain popularity not just in Europe and North America, but also in Asia.
With the increasing demand for sensor technology in Asia, IHS expects Chinese smartphone original equipment manufacturers (OEM) to be the next driver for a new generation of sensors.
Humidity sensors have been used in Chinese handsets since 2011. In the future, air-quality sensors will experience growing usage in China.
The first gas sensors have just been designed in by Chinese smartphone OEMs. IHS expects these phones will enter the market during the first half of 2015. There is also a specific demand for sensors that can detect particle pollution in large Chinese cities such as Beijing or Shanghai.
Extrasensory perception
In terms of revenue, fingerprint sensors now dominate the mobile market, followed by optical pulse sensors, humidity and UV sensors. IHS anticipates gas sensors will join the fray in 2015 and thermal imagers will arrive during the 2018 time period.
Thermal imagers using microbolometer sensors emerged from the technology of forward-looking infrared (FLIR) systems in 2014 as accessories for the iPhone 5s. However, it will take a few more years before these sensors decline enough in pricing to be embedded in smartphones.
IHS predicts that Samsung will adopt gas/chemical sensors in the Note 6 that will be introduced in 2016. This is because gas/chemical sensor technology will have matured and use cases will be more clearly defined by then.
Some sensors that have appeared in smartphones are likely to migrate to wearables, which in some cases are better platforms for health or environmental sensors.
Cadence announces broad portfolio of 3D memory verification IP
SAN JOSE, USA: Cadence Design Systems Inc. announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).
The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.
Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, VP of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, VP, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.
Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, VP of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, VP, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
Toshiba automotive infotainment companion chip supports high-res multimedia connectivity and camera devices
SAN JOSE, USA: Toshiba America Electronic Components Inc. (TAEC) has launched a key new addition to its extensive portfolio of solutions for the automotive market.
The TC358791XBG automotive companion chip was created to drive high-resolution multimedia (audio, video) and camera connectivity for next-generation infotainment applications in the connected car.
The new chip supports the latest automotive Gigabit Ethernet AVB standard for a wide range of applications, such as front/rear/surround-view cameras, digital audio and transferring high-resolution video content to head-unit and rear-seat entertainment systems.
The TC358791XBG can also seamlessly interface with and support many leading-edge automotive application processors on the market, thanks to its USB 3.0, MIPI® CSI-2 and DSI connectivity for both audio and video, and will support Automotive Electronics Council reliability specification AEC-Q100 (Grade 3).
The TC358791XBG can split one video input into two pictures and can simultaneously drive two high-resolution low-voltage differential signaling (LVDS) digital displays. Examples include head units, instrument clusters, and parking aid vision systems.
The chipset can also send high-resolution audio and video data from the host processor to multiple displays or other electronic control units in the car, and it has a High Definition Multimedia Interface (HDMI®) 1.4 receiver interface to allow connection of HDMI-enabled devices to the application processor.
The new chip is housed in a FBGA257 15mm x 15mm package with 0.8 mm ball pitch. Additional features include differential CVBS (composite) interfaces for analog composite video sources, support for early back-up camera view (CVBS to LVDS), and ability to relay packetized IQ audio tuner data to the host via USB.
The TC358791XBG automotive companion chip was created to drive high-resolution multimedia (audio, video) and camera connectivity for next-generation infotainment applications in the connected car.
The new chip supports the latest automotive Gigabit Ethernet AVB standard for a wide range of applications, such as front/rear/surround-view cameras, digital audio and transferring high-resolution video content to head-unit and rear-seat entertainment systems.
The TC358791XBG can also seamlessly interface with and support many leading-edge automotive application processors on the market, thanks to its USB 3.0, MIPI® CSI-2 and DSI connectivity for both audio and video, and will support Automotive Electronics Council reliability specification AEC-Q100 (Grade 3).
The TC358791XBG can split one video input into two pictures and can simultaneously drive two high-resolution low-voltage differential signaling (LVDS) digital displays. Examples include head units, instrument clusters, and parking aid vision systems.
The chipset can also send high-resolution audio and video data from the host processor to multiple displays or other electronic control units in the car, and it has a High Definition Multimedia Interface (HDMI®) 1.4 receiver interface to allow connection of HDMI-enabled devices to the application processor.
The new chip is housed in a FBGA257 15mm x 15mm package with 0.8 mm ball pitch. Additional features include differential CVBS (composite) interfaces for analog composite video sources, support for early back-up camera view (CVBS to LVDS), and ability to relay packetized IQ audio tuner data to the host via USB.
Z3 Technology's Z3-DM8107-SDI2-RPS development system delivers low power H.264 encoder solution
LINCOLN, USA: Providing the latest in integrated embedded solutions and products, Z3 Technology LLC announced today the immediate availability of the Z3-DM8107-SDI2-RPS broadcast encoder.
The encoder was developed as a video infrastructure solution that works in applications such as broadcast video encoding, medical video, video security and industrial DVR, and industrial video processing.
"With encoding capability of up to 1080p60 or dual channel with 1 channel of 1080i30 and 1 channel of 720p60, the Z3-DM8107-SDI2-RPS supports H.264 BP, MP and HP," says Aaron Caldwell, CEO, Z3 Technology. "ODM and OEM costs associated with development expenses and time-to-market are significantly reduced with Z3's application software that comes with our development kits."
As with all of Z3 Technology's Rapid Prototyping Systems, the Z3-DM8107-SDI2-RPS consists of a hardware package and software bundle designed to enable rapid development of multimedia applications.
Based on the DaVinci TMS320DM8107 video processor from Texas Instruments (TI), the hardware provided includes one Z3-DM8107-MOD-0x system-on-module card and a video infrastructure application board, Z3-DM8107-APP-2x, which provides advanced video input/output capabilities.
Measuring only 82mm x 43mm, the Z3-DM8107-MOD-0x is a compact OEM-ready module and features an ARM Cortex-A8 core capable of 750MHz, parallel and serial CMOS sensor ports, dual GigE ports, two SATA2 interfaces, PCI Express and 1GB DDR3 on board as well as 256MB of Flash.
This module offers low power consumption and H.264 1080p60 performance. The Z3-DM8107-MOD-0x is designed for applications such as digital video recorders (DVR), network video recorders (NVR), industrial video interface displays and medical imaging.
Z3's custom video infrastructure application board, Z3-DM8107-APP-2x, is included with the Z3-DM8107-SDI2-RPS system. This application board leverages the I/O expansion capability of the Z3-DM8107-MOD-0x to implement additional functions not present in the base module.
The Z3-DMI8107-SDI2-RPS includes inputs for 3G-SDI, HDMI, composite and analog stereo audio. The application board also has HDMI output. Gigabit Ethernet, USB 2.0 and RS-232 comprise the remaining interfaces on the Z3-DM8107-APP-2x.
The encoder was developed as a video infrastructure solution that works in applications such as broadcast video encoding, medical video, video security and industrial DVR, and industrial video processing.
"With encoding capability of up to 1080p60 or dual channel with 1 channel of 1080i30 and 1 channel of 720p60, the Z3-DM8107-SDI2-RPS supports H.264 BP, MP and HP," says Aaron Caldwell, CEO, Z3 Technology. "ODM and OEM costs associated with development expenses and time-to-market are significantly reduced with Z3's application software that comes with our development kits."
As with all of Z3 Technology's Rapid Prototyping Systems, the Z3-DM8107-SDI2-RPS consists of a hardware package and software bundle designed to enable rapid development of multimedia applications.
Based on the DaVinci TMS320DM8107 video processor from Texas Instruments (TI), the hardware provided includes one Z3-DM8107-MOD-0x system-on-module card and a video infrastructure application board, Z3-DM8107-APP-2x, which provides advanced video input/output capabilities.
Measuring only 82mm x 43mm, the Z3-DM8107-MOD-0x is a compact OEM-ready module and features an ARM Cortex-A8 core capable of 750MHz, parallel and serial CMOS sensor ports, dual GigE ports, two SATA2 interfaces, PCI Express and 1GB DDR3 on board as well as 256MB of Flash.
This module offers low power consumption and H.264 1080p60 performance. The Z3-DM8107-MOD-0x is designed for applications such as digital video recorders (DVR), network video recorders (NVR), industrial video interface displays and medical imaging.
Z3's custom video infrastructure application board, Z3-DM8107-APP-2x, is included with the Z3-DM8107-SDI2-RPS system. This application board leverages the I/O expansion capability of the Z3-DM8107-MOD-0x to implement additional functions not present in the base module.
The Z3-DMI8107-SDI2-RPS includes inputs for 3G-SDI, HDMI, composite and analog stereo audio. The application board also has HDMI output. Gigabit Ethernet, USB 2.0 and RS-232 comprise the remaining interfaces on the Z3-DM8107-APP-2x.
Accelerate control systems and increase integration while decreasing system cost with TI's C2000 Piccolo F2807x MCUs
HOUSTON, USA: Need a microcontroller (MCU) that allows you to quickly double system performance without doubling your cost or changing your hardware or software design?
With the powerful combination of the C28x CPU and accelerators, the new C2000 Piccolo F2807x MCUs from Texas Instruments (TI) boost execution speeds of control tasks in industrial applications such as telecom rectifiers, server power, solar micro inverters, frequency inverters and automotive HEV/EV.
The F2807x MCUs also provide many analog and control peripherals to enable more integrated control applications. They are scalable with the previously announced C2000 Delfino F2837xS and F2837xD MCU generations.
Designers looking to tap into the performance of the C2000 Piccolo F2807x MCUs can leverage the real-time control accelerator (CLA). The CLA doubles the throughput of the F2807x MCU, providing an additional 120 MHz of floating-point processing capability. This additional bandwidth allows designers to run parallel math-intensive or time-sensitive signal processing tasks.
Offloading these tasks to the CLA enables the CPU to focus on general system tasks such as diagnostics, communications, motion profiling and more. Also integrated in the main C28x CPU is a trigonometric math unit (TMU) accelerator, which enables the chip to quickly execute trigonometric-based algorithms used in transforms and control functions.
TI's C2000 Piccolo F2807x MCUs are also packed with high-end, smart analog and control integration — including a flexible, enhanced pulse-width modulator (PWM) that supports all digital power topologies — to decrease digital control system complexity. Three 12-bit ADCs increase sampling throughput by allowing designers to do simultaneous tasks such as monitor voltages and currents of three-phase motors while simultaneously decoding high-frequency resolver feedback.
Additionally, the F2807x MCUs can simultaneously process eight delta-sigma modulated channels, each with threshold comparators and a seamless interface to the TI AMC1204 isolated delta-sigma modulator, for isolated current and voltage measurements. Window comparators provide critical power stage protection.
With the powerful combination of the C28x CPU and accelerators, the new C2000 Piccolo F2807x MCUs from Texas Instruments (TI) boost execution speeds of control tasks in industrial applications such as telecom rectifiers, server power, solar micro inverters, frequency inverters and automotive HEV/EV.
The F2807x MCUs also provide many analog and control peripherals to enable more integrated control applications. They are scalable with the previously announced C2000 Delfino F2837xS and F2837xD MCU generations.
Designers looking to tap into the performance of the C2000 Piccolo F2807x MCUs can leverage the real-time control accelerator (CLA). The CLA doubles the throughput of the F2807x MCU, providing an additional 120 MHz of floating-point processing capability. This additional bandwidth allows designers to run parallel math-intensive or time-sensitive signal processing tasks.
Offloading these tasks to the CLA enables the CPU to focus on general system tasks such as diagnostics, communications, motion profiling and more. Also integrated in the main C28x CPU is a trigonometric math unit (TMU) accelerator, which enables the chip to quickly execute trigonometric-based algorithms used in transforms and control functions.
TI's C2000 Piccolo F2807x MCUs are also packed with high-end, smart analog and control integration — including a flexible, enhanced pulse-width modulator (PWM) that supports all digital power topologies — to decrease digital control system complexity. Three 12-bit ADCs increase sampling throughput by allowing designers to do simultaneous tasks such as monitor voltages and currents of three-phase motors while simultaneously decoding high-frequency resolver feedback.
Additionally, the F2807x MCUs can simultaneously process eight delta-sigma modulated channels, each with threshold comparators and a seamless interface to the TI AMC1204 isolated delta-sigma modulator, for isolated current and voltage measurements. Window comparators provide critical power stage protection.
SMIC and Maxscend collaborate on 55nm RF IP platform
SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. (SMIC) and Maxscend Technologies Inc., a RF IP company based in China, announced that Maxscend Bluetooth RF IP has been silicon proven on SMIC's 55nm Low Leakage (LL) logic process. This IP has now been integrated into one of SMIC customers' product tape-out.
The silicon proven Bluetooth RF IP is the result of a collaborative effort between SMIC and Maxscend and marks a significant milestone in SMIC RF IP platform setup. It has achieved a leading edge position in the industry and will provide mutual customers an excellent IP solution for the booming IoT market, as well as the prosperous mobile and tablet markets.
Dr. Tianshen Tang, senior VP of SMIC Design Service Center, commented: "We are pleased to be working with Maxscend. This important breakthrough will enable SMIC to offer leading 55nm RF IP solutions and secure SMIC's leading position in China's semiconductor foundry industry. We are confident that we can provide top quality solutions and design services for the customer."
"It is really exciting to see that our Bluetooth and BLE RF IP has been silicon proven on SMIC 55nm platform," said Zhihan Xu, CEO of Maxscend.
"Besides the current huge demand of smart-phones, tablets, Bluetooth Audio and other areas of traditional Bluetooth technologies, there is tremendous interest coming from low-power Bluetooth in the IoT field. With the wide adoption of Bluetooth low energy technology, smart devices will become ubiquitous in everyday life: wearables, smart-home, smart-medical, smart-sports and many more. By partnering with SMIC, we are confident we have the capabilities to support global customers with superior Bluetooth technology and professional technical services."
The silicon proven Bluetooth RF IP is the result of a collaborative effort between SMIC and Maxscend and marks a significant milestone in SMIC RF IP platform setup. It has achieved a leading edge position in the industry and will provide mutual customers an excellent IP solution for the booming IoT market, as well as the prosperous mobile and tablet markets.
Dr. Tianshen Tang, senior VP of SMIC Design Service Center, commented: "We are pleased to be working with Maxscend. This important breakthrough will enable SMIC to offer leading 55nm RF IP solutions and secure SMIC's leading position in China's semiconductor foundry industry. We are confident that we can provide top quality solutions and design services for the customer."
"It is really exciting to see that our Bluetooth and BLE RF IP has been silicon proven on SMIC 55nm platform," said Zhihan Xu, CEO of Maxscend.
"Besides the current huge demand of smart-phones, tablets, Bluetooth Audio and other areas of traditional Bluetooth technologies, there is tremendous interest coming from low-power Bluetooth in the IoT field. With the wide adoption of Bluetooth low energy technology, smart devices will become ubiquitous in everyday life: wearables, smart-home, smart-medical, smart-sports and many more. By partnering with SMIC, we are confident we have the capabilities to support global customers with superior Bluetooth technology and professional technical services."
Renesas delivers enhanced user experience with integrated automotive cockpit solution
TOKYO, JAPAN: Renesas Electronics Corp. is enhancing the driving experience with robust new solutions for the integrated car cockpit.
As the newest member of Renesas’ state-of-the-art R-Car Series for automotive, the R-Car E2 automotive systems-on-chip (SoCs) and the new R-Car E2 software development board deliver optimized infotainment and display audio for entry-level integrated cockpit systems that support smartphone interoperability.
In combination with other Renesas R-Car Series devices, it helps achieve the scalability required to bridge the full range of integrated cockpit systems from entry-level to high-end models.
In an integrated cockpit, the converged system integrates and analyzes multiple streams of information and reports the results to the driver in an optimized format, which is increasingly delivered through interoperation with smartphones. This convergence is driving demand for higher level functionality and greater added value for entry-level applications.
As the newest member of Renesas’ state-of-the-art R-Car Series for automotive, the R-Car E2 automotive systems-on-chip (SoCs) and the new R-Car E2 software development board deliver optimized infotainment and display audio for entry-level integrated cockpit systems that support smartphone interoperability.
In combination with other Renesas R-Car Series devices, it helps achieve the scalability required to bridge the full range of integrated cockpit systems from entry-level to high-end models.
In an integrated cockpit, the converged system integrates and analyzes multiple streams of information and reports the results to the driver in an optimized format, which is increasingly delivered through interoperation with smartphones. This convergence is driving demand for higher level functionality and greater added value for entry-level applications.
Cadence intros automotive functional safety verification solution
SAN JOSE, USA: Cadence Design Systems Inc. has introduced its new automotive functional safety verification solution, which reduces the effort required by automotive designers to prepare for ISO 26262 compliance by up to 50 percent.
An expansion to the Cadence Incisive functional verification platform, the new fault injection and safety verification technologies help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level (TCL).
The integrated Cadence Incisive functional safety solution reduces the compliance effort by automating the time-intensive manual verification process of fault injection and result analysis for IP, System-on-Chip (SoC) and system designs. The solution includes the Incisive Functional Safety Simulator and the Functional Safety Analysis capability in the Incisive vManager™ solution.
The new simulator operates within the Incisive Enterprise Simulator compiled-code engine, boosting runtime performance up to 10x and providing the seamless reuse of the functional and mixed-signal verification environments to accelerate the time to develop safety verification versus the interpreted Incisive Verifault-XL engine traditionally used in functional safety simulation.
The ability of safety systems to detect faults is the critical measurement for ISO 26262 compliance. The Functional Safety Analysis capability allows the safety engineer to automatically generate a safety verification regression from the fault dictionary created by the simulator and enables the Incisive vManager solution to track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design.
By automating the tracking of these safety metrics, the Incisive functional safety solution automates man-years of effort, and provides the traceable audit trail needed in the systems design chain from semiconductor to OEM suppliers.
"Addressing functional safety challenges, particularly in automotive electronics, is critical for the success of system and semiconductor companies," said Charlie Huang, executive VP, Worldwide Field Operations and System & Verification Group at Cadence.
"By partnering with companies like Melexis who embrace functional safety today, Cadence is delivering a solution that enables engineers to more efficiently address one of the key requirements to proliferate fault-tolerant electronics in the automotive industry where the safety of consumers is paramount."
The Incisive Functional Safety Simulator and Functional Safety Analysis technologies are part of the Cadence System Development Suite (SDS), addressing the largest and most complex verification and hardware-software co-development challenges faced by semiconductor and system companies.
An expansion to the Cadence Incisive functional verification platform, the new fault injection and safety verification technologies help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level (TCL).
The integrated Cadence Incisive functional safety solution reduces the compliance effort by automating the time-intensive manual verification process of fault injection and result analysis for IP, System-on-Chip (SoC) and system designs. The solution includes the Incisive Functional Safety Simulator and the Functional Safety Analysis capability in the Incisive vManager™ solution.
The new simulator operates within the Incisive Enterprise Simulator compiled-code engine, boosting runtime performance up to 10x and providing the seamless reuse of the functional and mixed-signal verification environments to accelerate the time to develop safety verification versus the interpreted Incisive Verifault-XL engine traditionally used in functional safety simulation.
The ability of safety systems to detect faults is the critical measurement for ISO 26262 compliance. The Functional Safety Analysis capability allows the safety engineer to automatically generate a safety verification regression from the fault dictionary created by the simulator and enables the Incisive vManager solution to track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design.
By automating the tracking of these safety metrics, the Incisive functional safety solution automates man-years of effort, and provides the traceable audit trail needed in the systems design chain from semiconductor to OEM suppliers.
"Addressing functional safety challenges, particularly in automotive electronics, is critical for the success of system and semiconductor companies," said Charlie Huang, executive VP, Worldwide Field Operations and System & Verification Group at Cadence.
"By partnering with companies like Melexis who embrace functional safety today, Cadence is delivering a solution that enables engineers to more efficiently address one of the key requirements to proliferate fault-tolerant electronics in the automotive industry where the safety of consumers is paramount."
The Incisive Functional Safety Simulator and Functional Safety Analysis technologies are part of the Cadence System Development Suite (SDS), addressing the largest and most complex verification and hardware-software co-development challenges faced by semiconductor and system companies.
Wednesday, October 22, 2014
Semitech debuts single-chip, grid-connected signal controller for IoT apps
MELBOURNE, AUSTRALIA: Semitech Semiconductor, a provider of narrowband power line communication (N-PLC) solutions that enable the transformation of the electricity grid into a smart grid, announced its new SM2480.
A single-chip, grid-connected signal controller, the SM2480 is ideal for solar inverters, smart lighting LED ballasts, home and building automation and other SCADA (Supervisory Control and Data Acquisition), and grid-connected applications.
The SM2480 integrates standards-based universal N-PLC with analog signal monitoring, control functions and peripherals -- making it the first chip in the world to offer all of the functions required for grid-connected micro inverter implementation.
Integrating the connectivity function with the control functions significantly reduces the cost of a solar micro-inverter design, enabling a cost effective, power efficient and smaller system architecture, which is critical for the mass deployment of micro-inverter-based solar systems and smart ballasts.
Micro-inverters and smart street lighting controllers are key to more efficient energy generation and usage and have become increasingly important components of the smart grid.
Despite their many advantages, the market has been slow to adopt micro-inverters, primarily due to cost concerns. A single-chip micro-inverter provides a complete platform to implement all of the functions in both the control and the communication paths, enabling significant cost improvement and system simplification.
A single-chip, grid-connected signal controller, the SM2480 is ideal for solar inverters, smart lighting LED ballasts, home and building automation and other SCADA (Supervisory Control and Data Acquisition), and grid-connected applications.
The SM2480 integrates standards-based universal N-PLC with analog signal monitoring, control functions and peripherals -- making it the first chip in the world to offer all of the functions required for grid-connected micro inverter implementation.
Integrating the connectivity function with the control functions significantly reduces the cost of a solar micro-inverter design, enabling a cost effective, power efficient and smaller system architecture, which is critical for the mass deployment of micro-inverter-based solar systems and smart ballasts.
Micro-inverters and smart street lighting controllers are key to more efficient energy generation and usage and have become increasingly important components of the smart grid.
Despite their many advantages, the market has been slow to adopt micro-inverters, primarily due to cost concerns. A single-chip micro-inverter provides a complete platform to implement all of the functions in both the control and the communication paths, enabling significant cost improvement and system simplification.
Prozess announces Valin as new distributor partner for reveal
ST. LOUIS, USA: Prozess Technologie, an emerging leader in the process measurement tools industry, has announced Valin Corp., a privately held, employee-owned company providing technical solutions for the technology, energy, life sciences, natural resources, and transportation industries, as a distribution partner for their new innovative process measurement platform, the Reveal.
Valin sees immediate applications to better provide precision measurement solutions to their customers in the Petroleum, Pharmaceutical and Semiconductor industries.
“Valin is one of the most respected names in the business,” said William Buie, president and GM of Prozess. “Valin quickly recognized the impact that Reveal’s flexible platform can have on the industries they serve. Our innovative Reveal device further demonstrates Valin’s leadership in bringing advancements to their customers.”
Valin serves customers that are looking for precise measurement in real time, and the Reveal addresses this need. Currently, engineers have to take samples of various elements on the manufacturing line and have it tested in the lab.
This lack of real-time measurement can prevent thousands of hours of efficient production and leads to unavoidable costs. With the simplicity of operating the Reveal, specific elements can be monitored and adjusted immediately so as not to cause any delays.
“The Reveal represents another level of customer service we’re dedicated to providing,” said Joseph Nettemeyer, president and CEO, Valin. “Customers can find anyone to provide them with products and parts, but we take it a step further by providing knowledge. We now have the ability to give our customers a huge level of knowledge in a portable robust, unit.
Valin sees immediate applications to better provide precision measurement solutions to their customers in the Petroleum, Pharmaceutical and Semiconductor industries.
“Valin is one of the most respected names in the business,” said William Buie, president and GM of Prozess. “Valin quickly recognized the impact that Reveal’s flexible platform can have on the industries they serve. Our innovative Reveal device further demonstrates Valin’s leadership in bringing advancements to their customers.”
Valin serves customers that are looking for precise measurement in real time, and the Reveal addresses this need. Currently, engineers have to take samples of various elements on the manufacturing line and have it tested in the lab.
This lack of real-time measurement can prevent thousands of hours of efficient production and leads to unavoidable costs. With the simplicity of operating the Reveal, specific elements can be monitored and adjusted immediately so as not to cause any delays.
“The Reveal represents another level of customer service we’re dedicated to providing,” said Joseph Nettemeyer, president and CEO, Valin. “Customers can find anyone to provide them with products and parts, but we take it a step further by providing knowledge. We now have the ability to give our customers a huge level of knowledge in a portable robust, unit.
Flurry of M&As reshape automotive semiconductor supplier landscape
EL SEGUNDO, USA: Capped by last week’s announcement that Qualcomm Inc. would buy CSR PLC, the automotive semiconductor industry recently has been undergoing a wave of merger and acquisition (M&A) activity that has shaken up the competitive order of the market, according to IHS Technology.
In two major deals announced in August, Germany’s Infineon Technologies AG said it would acquire US-based International Rectifier Corp., while On Semiconductor Corp. sealed a deal to acquire fellow American firm Aptina Imaging Corp.
With the International Rectifier deal, Infineon bolstered its No. 2 rank in the global automotive semiconductor business and helped it to close the gap on the market leader, Renesas of Japan. Following the acquisition, Infineon trails Renesas by just $288 million, down from nearly $500 before Infineon bought International Rectifier, based on ranking data from 2013.
Meanwhile, the Aptina acquisition expanded On's automotive semiconductor revenue by $183 million, allowing On to move up one position to eighth place in the market, also based on 2013 ranking data.
The purchase of the UK’s CSR will allow California-based Qualcomm to enhance its market share. Qualcomm ranked No. 43 in 2013, while CSR came in at 23. The two companies combined would have ranked at No. 19 in 2013.
“While these three M&A deals differ in their specific goals and benefits, all have the same strategic objective: expanding market share in the lucrative business for semiconductors used in automobiles,” said Ahad Buksh, analyst for automotive semiconductors at IHS.
“The automotive supply is adding new infotainment, communications and driver-assist functionality at a rapid pace, causing related semiconductor revenue to rise 5 percent to reach $26 billion in 2013. Suppliers are buying up competitors to gain scale in the market, to add key capabilities and to capitalize on established customer relationships.”
In two major deals announced in August, Germany’s Infineon Technologies AG said it would acquire US-based International Rectifier Corp., while On Semiconductor Corp. sealed a deal to acquire fellow American firm Aptina Imaging Corp.
With the International Rectifier deal, Infineon bolstered its No. 2 rank in the global automotive semiconductor business and helped it to close the gap on the market leader, Renesas of Japan. Following the acquisition, Infineon trails Renesas by just $288 million, down from nearly $500 before Infineon bought International Rectifier, based on ranking data from 2013.
The purchase of the UK’s CSR will allow California-based Qualcomm to enhance its market share. Qualcomm ranked No. 43 in 2013, while CSR came in at 23. The two companies combined would have ranked at No. 19 in 2013.
“While these three M&A deals differ in their specific goals and benefits, all have the same strategic objective: expanding market share in the lucrative business for semiconductors used in automobiles,” said Ahad Buksh, analyst for automotive semiconductors at IHS.
“The automotive supply is adding new infotainment, communications and driver-assist functionality at a rapid pace, causing related semiconductor revenue to rise 5 percent to reach $26 billion in 2013. Suppliers are buying up competitors to gain scale in the market, to add key capabilities and to capitalize on established customer relationships.”
EV Group next-gen nanoimprint lithography technology targets photonics, LED and bio-engineered device production
ST. FLORIAN, AUSTRIA: EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced its SmartNIL™ large-area nanoimprint lithography (NIL) process.
Available on all EV Group NIL platforms, including mask aligners as well as the industry benchmark EVG®720 and newly available EVG®7200 UV-NIL systems, SmartNIL provides a low-cost, large-area and high-volume-manufacturing solution for a variety of advanced devices, including:
* Photonic-based devices such as light-emitting diodes (LEDs), lasers and photovoltaics.
* Micro arrays and nano-devices for medical devices and bioengineered applications.
* Advanced storage media, including newly emerging forms of non-volatile memory (NVM).
Available on all EV Group NIL platforms, including mask aligners as well as the industry benchmark EVG®720 and newly available EVG®7200 UV-NIL systems, SmartNIL provides a low-cost, large-area and high-volume-manufacturing solution for a variety of advanced devices, including:
* Photonic-based devices such as light-emitting diodes (LEDs), lasers and photovoltaics.
* Micro arrays and nano-devices for medical devices and bioengineered applications.
* Advanced storage media, including newly emerging forms of non-volatile memory (NVM).
Artesyn successfully tests first 100G technology
HONG KONG: Artesyn Embedded Technologies announced the successful testing of the industry’s first 100G ATCA technology.
This breakthrough will for the first time enable bandwidth-hungry next-generation applications in software defined networking (SDN) and network functions virtualization (NFV) deployments to achieve up to 4 Tb/s aggregate throughput in a single open standards-based bladed server system.
Working with connector manufacturer, ERNI, Artesyn has developed the critical technology components – the connector and backplane – that enable 100 Gb/s Ethernet connectivity in an ATCA shelf.
The technology will be available in Artesyn’s Centellis 8000 series systems later in the year and the first applications set to take advantage of this breakthtrough are SDN/NFV network security and optimization, where deep packet inspection techniques are used to process massive data flows in real time.
This breakthrough will for the first time enable bandwidth-hungry next-generation applications in software defined networking (SDN) and network functions virtualization (NFV) deployments to achieve up to 4 Tb/s aggregate throughput in a single open standards-based bladed server system.
Working with connector manufacturer, ERNI, Artesyn has developed the critical technology components – the connector and backplane – that enable 100 Gb/s Ethernet connectivity in an ATCA shelf.
The technology will be available in Artesyn’s Centellis 8000 series systems later in the year and the first applications set to take advantage of this breakthtrough are SDN/NFV network security and optimization, where deep packet inspection techniques are used to process massive data flows in real time.
DSP Group delivers HD voice and home automation utilizing Qualcomm Internet processor
LOS ALTOS, USA: DSP Group Inc. announced that its DCX81 DECT/CAT-iq/ULE (Ultra Low Energy) system on a chip (SoC) can be integrated in gateways based on the Qualcomm Internet processor (IPQ806x) from Qualcomm Atheros Inc., a subsidiary of Qualcomm Inc.
The solution will enable delivery of advanced cordless telephony features like multi-line, multi-call and multi-handset with enhanced HD voice.
DSP Group's cutting-edge DECT/CAT-iq/ULE SoC offers full home coverage, wideband audio (HD voice) and ULE support for home automation and security - all at an attractive cost/performance ratio. Supporting multiple lines and handsets and in-field software upgradability, DSP Group's DECT/CAT-iq/ULE SoC reference design enables home gateway developers to rapidly deliver products complying with the CAT-iq 2.0, 2.1 and 3.0 standards.
The solution will enable delivery of advanced cordless telephony features like multi-line, multi-call and multi-handset with enhanced HD voice.
DSP Group's cutting-edge DECT/CAT-iq/ULE SoC offers full home coverage, wideband audio (HD voice) and ULE support for home automation and security - all at an attractive cost/performance ratio. Supporting multiple lines and handsets and in-field software upgradability, DSP Group's DECT/CAT-iq/ULE SoC reference design enables home gateway developers to rapidly deliver products complying with the CAT-iq 2.0, 2.1 and 3.0 standards.
Microchip's digitally enhanced power analog controllers offer digital power supply flexibility
USA: Microchip Technology Inc. has announced its latest Digitally Enhanced Power Analog (DEPA) controllers – the MCP19118 and MCP19119 (MCP19118/9).
They provide simple yet effective analog PWM control for DC-DC synchronous buck converters up to 40V, with the configurability of a digital MCU. And they are the industry's first devices to combine 40V operation and PMBus communication interfaces.
These features enable quick power-conversion circuit development with an analog control loop that is programmable in the integrated 8-bit PIC® MCU core's firmware. This integration and flexibility is ideal for power-conversion applications, such as battery-charging, LED-driving, USB Power Delivery, point-of-load and automotive power supplies.
Along with the rapidly growing popularity of digitally controlled power supplies, due to their configurability for a variety of operating conditions and topologies, power system designers also have an increasing need for the ability to report telemetry and conduct two-way communication (typically for monitoring and fault reporting), via standard communication interfaces such as PMBus.
Additionally, the recently released USB charging specifications (USB Power Delivery and the USB type C connector) include variable charging voltages, which allow for rapid device charging, but add potentially difficult hardware requirements.
By integrating a supervisory microcontroller, the MCP19118/9 devices can create programmable power supplies. Key system settings – such as switching frequency (100 kHz to 1.6 MHz), current limits and voltage setpoints – can be adjusted on the fly during operation by issuing write commands to the registers in the device. One design can then be reused for additional applications, using firmware updates to change the configuration, which minimises design, production and inventory requirements across multiple platforms.
Additionally, the integrated MCU core can be used to monitor other parts of the application to sequence startup operations; intelligently manage faults, under-voltage or brown-out conditions; perform housekeeping functions; adjust power outputs in response to load requirements (such as battery charging or USB port power); and assist with the module's external interfaces (monitoring or delivering signals to the user or system).
With integrated linear regulators, PWM generators, ADCs, MOSFET drivers, analog error amplifiers and control-loop compensation, the MCP19118/9 devices provide a very compact circuit solution. Properly implemented, this system is capable of high conversion efficiency and excellent transient response for reduced system power losses, smaller heatsinks and longer battery life in portable applications. These DEPA devices can also provide data over the I2C interface, using customised SMBus or PMBus compatible commands.
They provide simple yet effective analog PWM control for DC-DC synchronous buck converters up to 40V, with the configurability of a digital MCU. And they are the industry's first devices to combine 40V operation and PMBus communication interfaces.
These features enable quick power-conversion circuit development with an analog control loop that is programmable in the integrated 8-bit PIC® MCU core's firmware. This integration and flexibility is ideal for power-conversion applications, such as battery-charging, LED-driving, USB Power Delivery, point-of-load and automotive power supplies.
Along with the rapidly growing popularity of digitally controlled power supplies, due to their configurability for a variety of operating conditions and topologies, power system designers also have an increasing need for the ability to report telemetry and conduct two-way communication (typically for monitoring and fault reporting), via standard communication interfaces such as PMBus.
Additionally, the recently released USB charging specifications (USB Power Delivery and the USB type C connector) include variable charging voltages, which allow for rapid device charging, but add potentially difficult hardware requirements.
By integrating a supervisory microcontroller, the MCP19118/9 devices can create programmable power supplies. Key system settings – such as switching frequency (100 kHz to 1.6 MHz), current limits and voltage setpoints – can be adjusted on the fly during operation by issuing write commands to the registers in the device. One design can then be reused for additional applications, using firmware updates to change the configuration, which minimises design, production and inventory requirements across multiple platforms.
Additionally, the integrated MCU core can be used to monitor other parts of the application to sequence startup operations; intelligently manage faults, under-voltage or brown-out conditions; perform housekeeping functions; adjust power outputs in response to load requirements (such as battery charging or USB port power); and assist with the module's external interfaces (monitoring or delivering signals to the user or system).
With integrated linear regulators, PWM generators, ADCs, MOSFET drivers, analog error amplifiers and control-loop compensation, the MCP19118/9 devices provide a very compact circuit solution. Properly implemented, this system is capable of high conversion efficiency and excellent transient response for reduced system power losses, smaller heatsinks and longer battery life in portable applications. These DEPA devices can also provide data over the I2C interface, using customised SMBus or PMBus compatible commands.
Actions Semiconductor debuts first 28nm OWL series chipset
ZHUHAI, CHINA: Actions Semiconductor Co. Ltd has debuted its latest innovative 28nm process based quad-core application processor offering for the tablet and OTT set-top box markets at Global Sources' China Sourcing Fair - Electronics & Components held October 11-14 at the Asia World-Expo in Hong Kong.
The latest application processor is a 28nm process enhancement of its 40nm process twin, the ATM7039, announced in September 2013. Initially, Actions will offer two solutions, the ATM7039s, which is pin to pin compatible with its predecessor, the ATM7039c (40nm version), along with a more compact and efficient version, the ATM7059.
Like their predecessor, the ATM7039s and the ATM7059 feature a quad-core ARM CortexTM A9 CPU, high performance, world-class PowerVR GPU core from Imagination Technologies, 2K by 4K super high resolution decoding including support of the newest international standard - high definition HVEC/H.265 video decoding.
However, the new application processor employs 28nm LP process technology instead of 40nm and Actions' fourth generation low power design achieving 1.6GhZ single CPU speed with much lower power consumption and die cost. The new member of OWL series family brings a greatly improved user experience, enhanced processing speed, longer battery life and will support the upcoming Android Lollipop operating system.
Targeted directly at low and mid-tier, high volume Android® tablet manufacturers, it is a highly attractive and cost-effective solution across the board in mainstream tablet design, OTT set-top boxes, smart monitors, ultrabooks, digital signage, and other cloud-connected devices.
The latest application processor is a 28nm process enhancement of its 40nm process twin, the ATM7039, announced in September 2013. Initially, Actions will offer two solutions, the ATM7039s, which is pin to pin compatible with its predecessor, the ATM7039c (40nm version), along with a more compact and efficient version, the ATM7059.
Like their predecessor, the ATM7039s and the ATM7059 feature a quad-core ARM CortexTM A9 CPU, high performance, world-class PowerVR GPU core from Imagination Technologies, 2K by 4K super high resolution decoding including support of the newest international standard - high definition HVEC/H.265 video decoding.
However, the new application processor employs 28nm LP process technology instead of 40nm and Actions' fourth generation low power design achieving 1.6GhZ single CPU speed with much lower power consumption and die cost. The new member of OWL series family brings a greatly improved user experience, enhanced processing speed, longer battery life and will support the upcoming Android Lollipop operating system.
Targeted directly at low and mid-tier, high volume Android® tablet manufacturers, it is a highly attractive and cost-effective solution across the board in mainstream tablet design, OTT set-top boxes, smart monitors, ultrabooks, digital signage, and other cloud-connected devices.
TI strengthens DSP and vision processing on its "Jacinto" family of infotainment processors
DETROIT, USA: Texas Instruments (TI) is adding signal processing functionality to its new DRA75x processors to enable customers to augment infotainment and pair informational advanced driver assistance systems (ADAS) features.
The combination of these two will allow customers to produce cars with digital cockpit integration as well as traditional infotainment features without compromising performance. The new DRA75x processors, "Jacinto 6 EP" and "Jacinto 6 Ex", both developed on the same architecture as other "Jacinto" devices, enable automotive manufacturers to scale their investment without additional R&D or significant Bill-of-Material (BOM) increase to deliver a diverse portfolio of products with hardware and software compatibility.
"Jacinto 6 EP" is a processing leader in the infotainment segment with 1.4GHz of digital signal processor (DSP) performance equivalent to 22 GFLOPS / 60 GMACS. Complete with all the features of the "Jacinto 6", the "Jacinto 6 EP" device provides additional peripherals and DSP horsepower to add features while controlling system cost.
"Jacinto 6 EP" lowers the BOM by incorporating additional USB, video input and PCIe interfaces required in certain infotainment systems with demanding IO requirements. A second TMS320C66x DSP core, delivering a total of 1.4 GHz of signal processing, can be used for image manipulation technologies such as dynamically stitching multiple cameras into a single, surround or overhead view.
Also, the additional DSP performance enables augmented radio configurations (multi-tuner, multi-modal configurations leveraging antenna diversity and background scanning), audio and speech processing, active noise control (ANC), voice recognition and a variety of other technologies.
Further scaling the platform, the "Jacinto 6 Ex" device provides additional performance and integration possibilities from the "Jacinto 6 EP" by offering two embedded vision engines (EVEs) for simultaneous informational ADAS and infotainment functionalities without compromising the performance of either system.
Informational ADAS describes capabilities such as object and pedestrian detection, augmented reality navigation and driver identification leveraging cameras both inside and outside the car to enhance the driving experience without actively controlling the vehicle. These capabilities can be leveraged in the center stack, programmable cluster and head's-up display systems.
The EVEs enable high-performance analytic and vision algorithms operating concurrently with the ARM®, GPU, DSP, multimedia and additional sub-systems offering un-encumbered performance unlike anything available on the market today. Both EVEs and associated software libraries put customers in control of their development by leveraging the flexible, programmable, high-performance EVE cores for analytics algorithms.
The combination of these two will allow customers to produce cars with digital cockpit integration as well as traditional infotainment features without compromising performance. The new DRA75x processors, "Jacinto 6 EP" and "Jacinto 6 Ex", both developed on the same architecture as other "Jacinto" devices, enable automotive manufacturers to scale their investment without additional R&D or significant Bill-of-Material (BOM) increase to deliver a diverse portfolio of products with hardware and software compatibility.
"Jacinto 6 EP" is a processing leader in the infotainment segment with 1.4GHz of digital signal processor (DSP) performance equivalent to 22 GFLOPS / 60 GMACS. Complete with all the features of the "Jacinto 6", the "Jacinto 6 EP" device provides additional peripherals and DSP horsepower to add features while controlling system cost.
"Jacinto 6 EP" lowers the BOM by incorporating additional USB, video input and PCIe interfaces required in certain infotainment systems with demanding IO requirements. A second TMS320C66x DSP core, delivering a total of 1.4 GHz of signal processing, can be used for image manipulation technologies such as dynamically stitching multiple cameras into a single, surround or overhead view.
Also, the additional DSP performance enables augmented radio configurations (multi-tuner, multi-modal configurations leveraging antenna diversity and background scanning), audio and speech processing, active noise control (ANC), voice recognition and a variety of other technologies.
Further scaling the platform, the "Jacinto 6 Ex" device provides additional performance and integration possibilities from the "Jacinto 6 EP" by offering two embedded vision engines (EVEs) for simultaneous informational ADAS and infotainment functionalities without compromising the performance of either system.
Informational ADAS describes capabilities such as object and pedestrian detection, augmented reality navigation and driver identification leveraging cameras both inside and outside the car to enhance the driving experience without actively controlling the vehicle. These capabilities can be leveraged in the center stack, programmable cluster and head's-up display systems.
The EVEs enable high-performance analytic and vision algorithms operating concurrently with the ARM®, GPU, DSP, multimedia and additional sub-systems offering un-encumbered performance unlike anything available on the market today. Both EVEs and associated software libraries put customers in control of their development by leveraging the flexible, programmable, high-performance EVE cores for analytics algorithms.
ROHM's general-purpose automotive MCU system power supplies for idling stop systems
KYOTO, JAPAN & SANTA CLARA, USA: ROHM Semiconductor has recently announced the development of system power supplies optimized for high-performance microcontrollers in a variety of automotive systems, from electronic power steering to fuel injection, including HEVs and EVs.
The newly developed BD39001EKV-C utilizes a proprietary boost-buck switching method that ensures stable voltage supply, even when the battery voltage drops during start–stop operation, while improving power conversion efficiency by up to 5 percent vs. conventional products.
In response to the continued standardization and advancements in the automotive industry a startup sequence setting function is included that can adapt to a variety of MCU specifications and requirements.
With the continuing trend towards platform standardization in the automotive industry comes a push to promote the use of common parts worldwide. This is expected to increase demand for versatile products that can suit a variety of requirements and support microcontrollers of all types – as well as high-performance devices and solutions optimized for customized dedicated power supplies and specific applications.
In addition, the need to minimize fuel consumption has led to the adoption of start-stop systems that stop the engine during idling and other brief stops in order to prevent wasteful fuel consumption. However, this requires countermeasures to prevent MCU malfunction due to battery voltage fluctuations caused by cranking when the engine is started again.
In response, ROHM quickly developed a versatile, standardized power supply IC capable of providing stable voltage during stop-stop operation. The BD39001EKV-C utilizes a leading-edge 0.35um BiCDMOS power process and takes advantage of ROHM's analog design expertise to achieve a wide input voltage range from 4V to an absolute maximum of 40V.
The newly developed BD39001EKV-C utilizes a proprietary boost-buck switching method that ensures stable voltage supply, even when the battery voltage drops during start–stop operation, while improving power conversion efficiency by up to 5 percent vs. conventional products.
In response to the continued standardization and advancements in the automotive industry a startup sequence setting function is included that can adapt to a variety of MCU specifications and requirements.
With the continuing trend towards platform standardization in the automotive industry comes a push to promote the use of common parts worldwide. This is expected to increase demand for versatile products that can suit a variety of requirements and support microcontrollers of all types – as well as high-performance devices and solutions optimized for customized dedicated power supplies and specific applications.
In addition, the need to minimize fuel consumption has led to the adoption of start-stop systems that stop the engine during idling and other brief stops in order to prevent wasteful fuel consumption. However, this requires countermeasures to prevent MCU malfunction due to battery voltage fluctuations caused by cranking when the engine is started again.
In response, ROHM quickly developed a versatile, standardized power supply IC capable of providing stable voltage during stop-stop operation. The BD39001EKV-C utilizes a leading-edge 0.35um BiCDMOS power process and takes advantage of ROHM's analog design expertise to achieve a wide input voltage range from 4V to an absolute maximum of 40V.
Spansion adds 96 MCUs to FM4 family for industrial IoT
SUNNYVALE, USA: Spansion Inc. has added 96 new products to the Spansion FM4 family of flexible microcontrollers (MCUs).
Based on the ARM Cortex®-M4F core, the new MCUs boast a 200 MHz operating frequency and support a diverse set of on-chip peripherals for enhanced human machine interfaces (HMIs) and machine-to-machine (M2M) communications.
The rich set of peripherals and large memory allow single-chip solutions for a wide variety of applications including factory automation, industrial Internet of Things (IoT), motor control, office automation, building management systems, smart meters, digital cameras and multi-function printers.
"With 200 MHz operating frequency and 2 MB flash, the S6E2C series MCUs support more than a dozen of the latest and most popular high-speed communications standards ideal for M2M communications and industrial IoT. The dual-bank flash array allows seamless over-the-air (OTA) in-application reprogramming," said Dhiraj Handa, senior VP and GM, Spansion Multi-Market Microcontroller Business.
"We also uniquely offer robust 5V I/O on a high-performance, large-memory MCU. This eases design since designers only need one regulator for a 5V MCU and can continue to use the 5V logic and power drivers common to industrial embedded applications."
Based on the ARM Cortex®-M4F core, the new MCUs boast a 200 MHz operating frequency and support a diverse set of on-chip peripherals for enhanced human machine interfaces (HMIs) and machine-to-machine (M2M) communications.
The rich set of peripherals and large memory allow single-chip solutions for a wide variety of applications including factory automation, industrial Internet of Things (IoT), motor control, office automation, building management systems, smart meters, digital cameras and multi-function printers.
"With 200 MHz operating frequency and 2 MB flash, the S6E2C series MCUs support more than a dozen of the latest and most popular high-speed communications standards ideal for M2M communications and industrial IoT. The dual-bank flash array allows seamless over-the-air (OTA) in-application reprogramming," said Dhiraj Handa, senior VP and GM, Spansion Multi-Market Microcontroller Business.
"We also uniquely offer robust 5V I/O on a high-performance, large-memory MCU. This eases design since designers only need one regulator for a 5V MCU and can continue to use the 5V logic and power drivers common to industrial embedded applications."
Himax announces Google second round investment decision
TAINAN, TAIWAN: Himax Technologies Inc., a leading supplier and fabless manufacturer of display drivers and other semiconductor products, announced that Google Inc. has decided not to exercise its previously issued purchase option to make an additional investment into Himax's subsidiary, Himax Display Inc.
Himax has been authorized by Google to make the following statement: "Google continues to work closely with Himax as a strategic partner on future technologies and products and will remain a board observer."
Subsequent to Google's first round investment in the company's HDI subsidiary in October 2013, Himax has formed a strategic partnership with Google whereby Himax is the provider of liquid crystal on silicon (LCOS) microdisplay technology that Google has recognized as the technology of choice for head-mounted displays (HMD) such as Google Glass.
Since the third quarter of 2013, HDI has been expanding capacity and further enhancing production capabilities to meet demand for our LCOS product line.
Himax has been authorized by Google to make the following statement: "Google continues to work closely with Himax as a strategic partner on future technologies and products and will remain a board observer."
Subsequent to Google's first round investment in the company's HDI subsidiary in October 2013, Himax has formed a strategic partnership with Google whereby Himax is the provider of liquid crystal on silicon (LCOS) microdisplay technology that Google has recognized as the technology of choice for head-mounted displays (HMD) such as Google Glass.
Since the third quarter of 2013, HDI has been expanding capacity and further enhancing production capabilities to meet demand for our LCOS product line.
Tuesday, October 21, 2014
Entegris extends VaporSorb filter line for advanced yield protection in semiconductor processing
BILLERICA, USA: Entegris Inc. announced a new product for its VaporSorb line of airborne molecular contamination (AMC) filters. The new filter was created as an "all-in-one," single-filter solution for capturing critical AMC in the chemical mechanical planarization process, or CMP, in semiconductor manufacturing.
VaporSorb, which is a leading brand of filter used in cleanroom environments and for process tools during key steps in manufacturing, is the first such filter available for CMP process tools that protects against weak acids as well as other contaminants.
The new filter was designed specifically for CMP tools to provide balanced lifetimes for all critical AMC in a single filter which avoids the complexities of multi-filter handling. In addition, the filter retains the VaporSorb brand's industry-leading service life to reduce both tool downtime and cost of ownership.
"Yield concerns in the CMP process, just as in the photolithography process, can be addressed by providing complete AMC protection. This means protecting against weak acids, as well as strong acids and other contaminants," stated Entegris Product Marketing manager for AMC Filtration Solutions, Marc Venet. "With VaporSorb CMP, we have a single solution that completely addresses AMC-induced corrosion defects in CMP processes."
Examples of weak acids include acetic and formic acids (acetate; CH3COO- and formate; HCOO-) and nitrous acid (nitrite; NO2-). Strong acids include HNO3, SO2, H2SO4 and HCl. These contaminants are causing concerns regarding defects and yield in CMP processes.
VaporSorb, which is a leading brand of filter used in cleanroom environments and for process tools during key steps in manufacturing, is the first such filter available for CMP process tools that protects against weak acids as well as other contaminants.
The new filter was designed specifically for CMP tools to provide balanced lifetimes for all critical AMC in a single filter which avoids the complexities of multi-filter handling. In addition, the filter retains the VaporSorb brand's industry-leading service life to reduce both tool downtime and cost of ownership.
"Yield concerns in the CMP process, just as in the photolithography process, can be addressed by providing complete AMC protection. This means protecting against weak acids, as well as strong acids and other contaminants," stated Entegris Product Marketing manager for AMC Filtration Solutions, Marc Venet. "With VaporSorb CMP, we have a single solution that completely addresses AMC-induced corrosion defects in CMP processes."
Examples of weak acids include acetic and formic acids (acetate; CH3COO- and formate; HCOO-) and nitrous acid (nitrite; NO2-). Strong acids include HNO3, SO2, H2SO4 and HCl. These contaminants are causing concerns regarding defects and yield in CMP processes.
SMIC certifies Synopsys IC Validator for signoff physical verification
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its IC Validator product has been certified by Semiconductor Manufacturing International Corp. (SMIC) for signoff physical verification of their 28-nanometer (nm) PolySiON (PS) manufacturing process.
This availability gives mutual customers access to a wider selection of leading signoff tools for physical verification. The fully qualified design rule checking (DRC) and layout-versus-schematic (LVS) runsets are available for download from the SMIC website.
"Formalizing our certification of IC Validator is a big step forward in supporting a number of our mutual customers for signoff verification. We are expanding our 28-nm pilot production through the end of 2014," said Dr. Waisum Wong, senior director of Technology Development at SMIC. "We expect that the 28-nm product life cycle longevity will exceed previous nodes, and we are pleased to include IC Validator as part of our signoff infrastructure."
IC Validator, part of the Synopsys Galaxy Design Platform, is a comprehensive solution for all physical verification tasks, including DRC, LVS, manufacturability enhancement, electrical rule checking (ERC) and metal fill insertion. Its modern architecture and excellent multi-core scalability make IC Validator the signoff tool of choice for a growing number of customers who are working on small analog designs, or large digital system-on-chip (SoC) designs.
Foundry-certified runsets enable Synopsys' In-Design physical verification with IC Compiler place and route and StarRC transistor-level parasitic extraction. IC Validator enables coding at higher levels of abstraction, which allows SMIC to streamline design rule development and deployment, and provide mutual customers with the high accuracy and excellent scalability needed for designs done on leading-edge process nodes.
"As manufacturing complexity places increased pressure on designers to deliver within tighter schedules, it is important that we continue to collaborate closely with foundries like SMIC," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "SMIC's certification demonstrates how designers with the most demanding designs are driving the market towards better signoff verification solutions that are also closely integrated into their design flows."
This availability gives mutual customers access to a wider selection of leading signoff tools for physical verification. The fully qualified design rule checking (DRC) and layout-versus-schematic (LVS) runsets are available for download from the SMIC website.
"Formalizing our certification of IC Validator is a big step forward in supporting a number of our mutual customers for signoff verification. We are expanding our 28-nm pilot production through the end of 2014," said Dr. Waisum Wong, senior director of Technology Development at SMIC. "We expect that the 28-nm product life cycle longevity will exceed previous nodes, and we are pleased to include IC Validator as part of our signoff infrastructure."
IC Validator, part of the Synopsys Galaxy Design Platform, is a comprehensive solution for all physical verification tasks, including DRC, LVS, manufacturability enhancement, electrical rule checking (ERC) and metal fill insertion. Its modern architecture and excellent multi-core scalability make IC Validator the signoff tool of choice for a growing number of customers who are working on small analog designs, or large digital system-on-chip (SoC) designs.
Foundry-certified runsets enable Synopsys' In-Design physical verification with IC Compiler place and route and StarRC transistor-level parasitic extraction. IC Validator enables coding at higher levels of abstraction, which allows SMIC to streamline design rule development and deployment, and provide mutual customers with the high accuracy and excellent scalability needed for designs done on leading-edge process nodes.
"As manufacturing complexity places increased pressure on designers to deliver within tighter schedules, it is important that we continue to collaborate closely with foundries like SMIC," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "SMIC's certification demonstrates how designers with the most demanding designs are driving the market towards better signoff verification solutions that are also closely integrated into their design flows."
Synopsys STAR Memory system multi-memory bus processor enables 10 percent die size reduction for Marvell SoC
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Marvell Semiconductor Inc. used Synopsys' DesignWare STAR Memory System's new multi-memory bus (MMB) processor to achieve a 10 percent reduction in total die size while maintaining product quality and performance for its networking system-on-chip (SoC).
Using the DesignWare STAR Memory System embedded test and repair solution, Marvell accelerated silicon bring-up and achieved silicon success.
Marvell's design includes hundreds of memory instances and required a test solution that would minimize area and routing congestion without affecting performance or quality.
The MMB processor in the DesignWare STAR Memory System contains all of the logic needed to implement a comprehensive test and repair strategy for all memory instances mapped on a multi-memory test bus. Marvell was able to use a single MMB processor to test hundreds of memories, saving over 50 percent in memory test logic area.
With the addition of the MMB processor to the STAR Memory System, designers now have the flexibility to either decouple test logic from the block under test or optimally place the test logic within the block to minimize the impact on performance and area. The MMB processor is ideally suited for high-performance design blocks and processor subsystems with L1 and L2 caches optimized for maximum performance.
"Using the DesignWare STAR Memory System has significantly reduced our silicon area and cost," said Sohail Syed, senior director of Engineering at Marvell.
"We were able to not only reduce total die size by 10 percent, but also meet our stringent product quality goals and high performance requirements by using the new MMB processor. In addition, the STAR Memory System's Yield Accelerator and Silicon Browser tools have significantly improved our silicon bring-up efforts by making test pattern development and validation more efficient."
The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to implement high test coverage, reduce design time, lower manufacturing test costs and maximize manufacturing yield.
Synopsys employs rigorous simulation and silicon characterization methods to identify prevalent memory defect mechanisms at every process node and then develops the test algorithms to detect them. Used in billions of chips, the STAR Memory System is a two-time winner of Test & Measurement World's prestigious "Best in Test" Award.
"Synopsys provides robust test solutions that enable designers to meet their challenging performance, power and area requirements without compromising on quality," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With the addition of the MMB processor in the DesignWare STAR Memory System, designers can reduce their on-die test footprint and maintain high performance while implementing comprehensive memory test solutions for faster time to volume."
Using the DesignWare STAR Memory System embedded test and repair solution, Marvell accelerated silicon bring-up and achieved silicon success.
Marvell's design includes hundreds of memory instances and required a test solution that would minimize area and routing congestion without affecting performance or quality.
The MMB processor in the DesignWare STAR Memory System contains all of the logic needed to implement a comprehensive test and repair strategy for all memory instances mapped on a multi-memory test bus. Marvell was able to use a single MMB processor to test hundreds of memories, saving over 50 percent in memory test logic area.
With the addition of the MMB processor to the STAR Memory System, designers now have the flexibility to either decouple test logic from the block under test or optimally place the test logic within the block to minimize the impact on performance and area. The MMB processor is ideally suited for high-performance design blocks and processor subsystems with L1 and L2 caches optimized for maximum performance.
"Using the DesignWare STAR Memory System has significantly reduced our silicon area and cost," said Sohail Syed, senior director of Engineering at Marvell.
"We were able to not only reduce total die size by 10 percent, but also meet our stringent product quality goals and high performance requirements by using the new MMB processor. In addition, the STAR Memory System's Yield Accelerator and Silicon Browser tools have significantly improved our silicon bring-up efforts by making test pattern development and validation more efficient."
The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to implement high test coverage, reduce design time, lower manufacturing test costs and maximize manufacturing yield.
Synopsys employs rigorous simulation and silicon characterization methods to identify prevalent memory defect mechanisms at every process node and then develops the test algorithms to detect them. Used in billions of chips, the STAR Memory System is a two-time winner of Test & Measurement World's prestigious "Best in Test" Award.
"Synopsys provides robust test solutions that enable designers to meet their challenging performance, power and area requirements without compromising on quality," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With the addition of the MMB processor in the DesignWare STAR Memory System, designers can reduce their on-die test footprint and maintain high performance while implementing comprehensive memory test solutions for faster time to volume."
DSP Group intros ULE for IoT applications over Intel Puma six-powered home gateways
LOS ALTOS, USA: DSP Group Inc., a leading global provider of wireless chipset solutions for converged communications, announced the integration of its ULE-based chipset with home gateways based on Intel's Puma 6 SoC.
The solution uses DSP Group's advanced DECT / ULE SoC integrated with the Intel Puma platform.
DSP Group's cutting-edge ULE solution provides full home coverage on a dedicated interference-free RF spectrum. In addition, the ULE-based solution enables rich voice and visual content to be transferred from nodes to the base and vice versa, providing a unique IoT solution that is unparalleled by other short range RF technology.
The ULE solution is easily software-upgradable from standard DECT, which already exists in over than 25 million home gateways. This eliminates the need to add a second OTT (Over-the-Top) box - reducing overall service provider OPEX.
The solution uses DSP Group's advanced DECT / ULE SoC integrated with the Intel Puma platform.
DSP Group's cutting-edge ULE solution provides full home coverage on a dedicated interference-free RF spectrum. In addition, the ULE-based solution enables rich voice and visual content to be transferred from nodes to the base and vice versa, providing a unique IoT solution that is unparalleled by other short range RF technology.
The ULE solution is easily software-upgradable from standard DECT, which already exists in over than 25 million home gateways. This eliminates the need to add a second OTT (Over-the-Top) box - reducing overall service provider OPEX.
NA semiconductor equipment industry posts Sept. 2014 book-to-bill ratio of 0.94
SAN JOSE, USA: North America-based manufacturers of semiconductor equipment posted $1.17 billion in orders worldwide in September 2014 (three-month average basis) and a book-to-bill ratio of 0.94, according to the September EMDS Book-to-Bill Report published by SEMI.
A book-to-bill of 0.94 means that $94 worth of orders were received for every $100 of product billed for the month.
The three-month average of worldwide bookings in September 2014 was $1.17 billion. The bookings figure is 12.9 percent lower than the final August 2014 level of $1.35 billion, and is 18.1 percent higher than the September 2013 order level of $992.8 million.
The three-month average of worldwide billings in September 2014 was $1.25 billion. The billings figure is 3.3 percent lower than the final August 2014 level of $1.29 billion, and is 22.5 percent higher than the September 2013 billings level of $1.02 billion.
“Following 11 months of above parity book-to-bill ratios, the three-month average ratio declined in September,” said Denny McGuirk, president and CEO of SEMI. "While order activity moderated, equipment spending this year is expected to be robust and remain on pace for double-digit year-over-year growth.”
A book-to-bill of 0.94 means that $94 worth of orders were received for every $100 of product billed for the month.
The three-month average of worldwide bookings in September 2014 was $1.17 billion. The bookings figure is 12.9 percent lower than the final August 2014 level of $1.35 billion, and is 18.1 percent higher than the September 2013 order level of $992.8 million.
The three-month average of worldwide billings in September 2014 was $1.25 billion. The billings figure is 3.3 percent lower than the final August 2014 level of $1.29 billion, and is 22.5 percent higher than the September 2013 billings level of $1.02 billion.
“Following 11 months of above parity book-to-bill ratios, the three-month average ratio declined in September,” said Denny McGuirk, president and CEO of SEMI. "While order activity moderated, equipment spending this year is expected to be robust and remain on pace for double-digit year-over-year growth.”
Micromem and Castrol innoVentures sign joint development agreement
TORONTO, CANADA & NEW YORK, USA: Micromem Technologies Inc., through its wholly owned subsidiary Micromem Applied Sensor Technologies Inc. (MAST), has executed a Joint Product Development Agreement with Castrol innoVentures.
Castrol innoVentures is Castrol's innovation and venturing arm. It seeks to invest in and create material businesses beyond lubricants.
The principal objective outlined in the Agreement will have the company provide Castrol with its MEMS-based sensor solution that could be deployed into operational environments to provide Castrol with real time performance data.
The intellectual property associated with the product development will be licensed exclusively to Castrol as part of a long term sales based royalty arrangement. Castrol will be responsible for sales and marketing of the new product into their existing global markets.
Castrol innoVentures is Castrol's innovation and venturing arm. It seeks to invest in and create material businesses beyond lubricants.
The principal objective outlined in the Agreement will have the company provide Castrol with its MEMS-based sensor solution that could be deployed into operational environments to provide Castrol with real time performance data.
The intellectual property associated with the product development will be licensed exclusively to Castrol as part of a long term sales based royalty arrangement. Castrol will be responsible for sales and marketing of the new product into their existing global markets.
Monday, October 20, 2014
GlobalFoundries to acquire IBM's microelectronics business
ARMONK & SANTA CLARA, USA: IBM and GLOBALFOUNDRIES have signed a Definitive Agreement under which GLOBALFOUNDRIES plans to acquire IBM's global commercial semiconductor technology business, including intellectual property, world-class technologists and technologies related to IBM Microelectronics, subject to completion of applicable regulatory reviews.
GLOBALFOUNDRIES will also become IBM's exclusive server processor semiconductor technology provider for 22 nanometer (nm), 14nm and 10nm semiconductors for the next 10 years.
The Agreement, once closed, enables IBM to further focus on fundamental semiconductor research and the development of future cloud, mobile, big data analytics, and secure transaction-optimized systems.
IBM continues its previously announced $3 billion investment over five years for semiconductor technology research to lead in the next generation of computing. GLOBALFOUNDRIES will have primary access to the research that results from this investment through joint collaboration at the Colleges of Nanoscale Science and Engineering (CNSE), SUNY Polytechnic Institute, in Albany, N.Y.
As part of this Agreement, GLOBALFOUNDRIES will gain substantial intellectual property including thousands of patents, making GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.
GLOBALFOUNDRIES also will benefit from an influx of one of the best technical teams in the semiconductor industry, which will solidify its path to advanced process geometries at 10nm and below. Additionally, the acquisition opens up business opportunities in industry-leading radio frequency (RF) and specialty technologies and ASIC design capabilities.
"This acquisition solidifies GLOBALFOUNDRIES' leadership position in semiconductor technology development and manufacturing,” said Dr. Sanjay Jha, CEO, GLOBALFOUNDRIES.
“We can now offer our customers a broader range of differentiated leading-edge 3D transistor and RF technologies, and we will also improve our design ecosystem to accelerate time-to-revenue for our customers. This acquisition further strengthens advanced manufacturing in the United States, and builds on established relationships in New York and Vermont.”
“The Agreement expands our longstanding collaboration, which began when GLOBALFOUNDRIES was created in 2009, and reflects our confidence in GLOBALFOUNDRIES’ capability,” said IBM senior VP and director of Research Dr. John E. Kelly III.
"This acquisition enables IBM to focus on fundamental semiconductor and material science research, development capabilities and expertise in high-value systems, with GLOBALFOUNDRIES' leadership in advanced technology manufacturing at scale and commitment to delivering future semiconductor technologies. We are grateful for the leadership and investments by the states of New York and Vermont in supporting the semiconductor industry.”
This acquisition bolsters semiconductor manufacturing and technology development in the United States. GLOBALFOUNDRIES has robust capital expenditure plans of approximately $10 billion in 2014-2015, with the majority being invested in New York. GLOBALFOUNDRIES has created nearly 3,000 direct jobs in New York and thousands more indirect jobs in the United States since 2009.
GLOBALFOUNDRIES will acquire and operate existing IBM semiconductor manufacturing operations and facilities in East Fishkill, New York and Essex Junction, Vermont, adding capacity to serve its customers and thousands of jobs to GLOBALFOUNDRIES' workforce.
GLOBALFOUNDRIES plans to provide employment opportunities for substantially all IBM employees at the two facilities who are part of the transferred businesses, except for a team of semiconductor server group employees who will remain with IBM. After the close of this transaction, GLOBALFOUNDRIES will be the largest semiconductor technology manufacturing employer in the Northeast.
GLOBALFOUNDRIES will also acquire IBM's commercial microelectronics business, which includes ASIC and specialty foundry, manufacturing and related operations and sales. GLOBALFOUNDRIES plans to invest to grow these businesses.
GLOBALFOUNDRIES will also become IBM's exclusive server processor semiconductor technology provider for 22 nanometer (nm), 14nm and 10nm semiconductors for the next 10 years.
The Agreement, once closed, enables IBM to further focus on fundamental semiconductor research and the development of future cloud, mobile, big data analytics, and secure transaction-optimized systems.
IBM continues its previously announced $3 billion investment over five years for semiconductor technology research to lead in the next generation of computing. GLOBALFOUNDRIES will have primary access to the research that results from this investment through joint collaboration at the Colleges of Nanoscale Science and Engineering (CNSE), SUNY Polytechnic Institute, in Albany, N.Y.
As part of this Agreement, GLOBALFOUNDRIES will gain substantial intellectual property including thousands of patents, making GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.
GLOBALFOUNDRIES also will benefit from an influx of one of the best technical teams in the semiconductor industry, which will solidify its path to advanced process geometries at 10nm and below. Additionally, the acquisition opens up business opportunities in industry-leading radio frequency (RF) and specialty technologies and ASIC design capabilities.
"This acquisition solidifies GLOBALFOUNDRIES' leadership position in semiconductor technology development and manufacturing,” said Dr. Sanjay Jha, CEO, GLOBALFOUNDRIES.
“We can now offer our customers a broader range of differentiated leading-edge 3D transistor and RF technologies, and we will also improve our design ecosystem to accelerate time-to-revenue for our customers. This acquisition further strengthens advanced manufacturing in the United States, and builds on established relationships in New York and Vermont.”
“The Agreement expands our longstanding collaboration, which began when GLOBALFOUNDRIES was created in 2009, and reflects our confidence in GLOBALFOUNDRIES’ capability,” said IBM senior VP and director of Research Dr. John E. Kelly III.
"This acquisition enables IBM to focus on fundamental semiconductor and material science research, development capabilities and expertise in high-value systems, with GLOBALFOUNDRIES' leadership in advanced technology manufacturing at scale and commitment to delivering future semiconductor technologies. We are grateful for the leadership and investments by the states of New York and Vermont in supporting the semiconductor industry.”
This acquisition bolsters semiconductor manufacturing and technology development in the United States. GLOBALFOUNDRIES has robust capital expenditure plans of approximately $10 billion in 2014-2015, with the majority being invested in New York. GLOBALFOUNDRIES has created nearly 3,000 direct jobs in New York and thousands more indirect jobs in the United States since 2009.
GLOBALFOUNDRIES will acquire and operate existing IBM semiconductor manufacturing operations and facilities in East Fishkill, New York and Essex Junction, Vermont, adding capacity to serve its customers and thousands of jobs to GLOBALFOUNDRIES' workforce.
GLOBALFOUNDRIES plans to provide employment opportunities for substantially all IBM employees at the two facilities who are part of the transferred businesses, except for a team of semiconductor server group employees who will remain with IBM. After the close of this transaction, GLOBALFOUNDRIES will be the largest semiconductor technology manufacturing employer in the Northeast.
GLOBALFOUNDRIES will also acquire IBM's commercial microelectronics business, which includes ASIC and specialty foundry, manufacturing and related operations and sales. GLOBALFOUNDRIES plans to invest to grow these businesses.
Synopsys intros industry's first on-chip memory test and repair solution for embedded flash
MOUNTAIN VIEW, USA: Synopsys Inc. introduced the DesignWare STAR Memory System® for Embedded Flash product, the industry's first integrated memory test and repair solution with test algorithms optimized for on-chip embedded flash memories.
The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to improve test coverage, reduce design time, lower test costs and maximize manufacturing yield. The STAR Memory System for Embedded Flash is a built-in self-test (BIST) solution that tests for the failure mechanisms associated with embedded flash memories, reducing overall integration time and cutting associated test costs by 20 percent compared to external solutions.
Embedded flash memories are increasingly used with microcontrollers in system-on-chips (SoCs) for Internet of Things (IoT) wearables, smart appliances and automotive safety systems, which have stringent cost and reliability requirements.
"Synopsys' DesignWare STAR Memory System for Embedded Flash is a valuable product for chip designers utilizing our highly popular 55-nanometer process, which has already been widely adopted for numerous IoT applications," said Shih Chin Lin, senior director of IP development and design support division at UMC.
"This solution provides our mutual customers with integrated test and repair capabilities that reduce overall design effort and lower test costs. Designers who are taking advantage of our 55-nanometer eFlash process will find that the post-silicon debug and analysis capabilities of Synopsys' Yield Accelerator and Silicon Browser will make designers' product characterization and validation efforts even more efficient."
The STAR Memory System for Embedded Flash offers in-field diagnostic capabilities to identify issues during system operation. With these capabilities, memory issues can be diagnosed even after the devices have shipped to the end customer.
The STAR Memory System allows hierarchical generation and verification of the test and repair IP to be inserted into the SoC while maintaining the original design hierarchy. This can reduce integration effort and SoC development time by allowing reuse of existing design constraints and configuration files.
Additionally, the post-silicon Yield Accelerator and Silicon Browser features can reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months. Used in billions of chips, the STAR Memory System is a two-time winner of Test & Measurement World's prestigious "Best in Test" Award.
"SoC designers for IoT and automotive devices must implement cost-effective features that enable efficient test and diagnostics for the full life cycle of their products," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Testing embedded flash memories has historically required expensive external test solutions. With STAR Memory System for Embedded Flash, designers can reduce their test cost and development schedules, getting their products to market faster."
The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to improve test coverage, reduce design time, lower test costs and maximize manufacturing yield. The STAR Memory System for Embedded Flash is a built-in self-test (BIST) solution that tests for the failure mechanisms associated with embedded flash memories, reducing overall integration time and cutting associated test costs by 20 percent compared to external solutions.
Embedded flash memories are increasingly used with microcontrollers in system-on-chips (SoCs) for Internet of Things (IoT) wearables, smart appliances and automotive safety systems, which have stringent cost and reliability requirements.
"Synopsys' DesignWare STAR Memory System for Embedded Flash is a valuable product for chip designers utilizing our highly popular 55-nanometer process, which has already been widely adopted for numerous IoT applications," said Shih Chin Lin, senior director of IP development and design support division at UMC.
"This solution provides our mutual customers with integrated test and repair capabilities that reduce overall design effort and lower test costs. Designers who are taking advantage of our 55-nanometer eFlash process will find that the post-silicon debug and analysis capabilities of Synopsys' Yield Accelerator and Silicon Browser will make designers' product characterization and validation efforts even more efficient."
The STAR Memory System for Embedded Flash offers in-field diagnostic capabilities to identify issues during system operation. With these capabilities, memory issues can be diagnosed even after the devices have shipped to the end customer.
The STAR Memory System allows hierarchical generation and verification of the test and repair IP to be inserted into the SoC while maintaining the original design hierarchy. This can reduce integration effort and SoC development time by allowing reuse of existing design constraints and configuration files.
Additionally, the post-silicon Yield Accelerator and Silicon Browser features can reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months. Used in billions of chips, the STAR Memory System is a two-time winner of Test & Measurement World's prestigious "Best in Test" Award.
"SoC designers for IoT and automotive devices must implement cost-effective features that enable efficient test and diagnostics for the full life cycle of their products," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Testing embedded flash memories has historically required expensive external test solutions. With STAR Memory System for Embedded Flash, designers can reduce their test cost and development schedules, getting their products to market faster."
Subscribe to:
Posts (Atom)
