Reflex CES enters mainstream FPGA-prototyping market

FRANCE: Reflex CES, a provider of custom embedded and complex systems, introduced the FPP25, a fast ASIC/SOC prototyping platform for emulating designs of up to 25-million ASIC gates using a stand-alone system.

Based on Xilinx Virtex-7 2000T FPGAs, FPP25 exploits Reflex CES’ collaboration with Flexras, an EDA company specializing in FPGA design partitioning software, and Adacsys, a functional verification software provider, to offer design engineers an easy-to-use, next generation platform to speed up validation and verification of complex, high density digital designs.

FPP25 will be showcased at Embedded World 2013, Nuremberg, Germany, February, 26-28, Hall 1, Booth 1-103.

“The FPP25 is the result of combining Reflex CES’s expertise in the design of complex electronic boards and Xilinx’s industry-leading Virtex-7 All Programmable FPGAs, reflecting the strong relationship between Reflex CES and Xilinx,” said Giles Peckham, EMEA director of Marketing, Xilinx.

“Our collaboration with established software suppliers like Flexras and Adacsys and our expertise and experience developing circuit boards using FPGAs and high speed interfaces allows us to confidently enter the mainstream FPGA-based prototyping market with a solution that improves the verification of ASICs and SOCs, their associated IP cores and applications software,” noted Sylvain Neveu, Reflex CES co-founder and COO.

FPP25 integrates Flexras Wasga automatic partitioning design suite offering high performance partitioning, timing analysis and high-speed pin-multiplexing solutions to improve design productivity. The Reflex CES FPP25 prototyping platform can optionally add Adacsys AVA (Advanced Verification Acceleration) software for advanced verification as well as Xilinx Vivado Design Suite and Xilinx ChipScope debugging tools.

The FPP25 prototyping platform operates with a GbE interface, a USB interface or a 4-lane PCIe cable (GEN2). A single FPP25 platform can emulate up to 25-million ASIC gates using three high density Virtex-7 FPGAs (two XC7V2000Ts and one XC7VX485T) that are 100 percent available to user applications.

Each Virtex-7 2000T FPGA intercommunicates by nearly 400 LVDS signals at 1.25Gbps. An onboard CPU with an embedded Linux operating system is implemented to handle the configuration and monitoring functions. FPP25 platforms can be chained together (up to 5 platforms) to address high density designs of over 125 million ASIC gates.

FPP25 prototyping platforms are now available from Reflex CES with reference designs, a user’s guide, and the Flexras Wasga automatic partitioning software. Adacsys AVA software for design verification is available as an option.