Calypto’s Catapult integrates with Real Intent’s Ascent Lint for reliable RTL implementation flow

USA: Calypto Design Systems Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, and Real Intent Inc., the leading provider of software products that accelerate early functional verification and advanced sign-off of electronic designs, announced the integration of Calypto’s Catapult high-level synthesis tool and Real Intent’s Ascent Lint product.

The resulting solution ensures Catapult-generated RTL code is lint clean and error free for a safe and reliable implementation flow from RTL to GDSII layout.

“A key requirement for our customers is to seamlessly fit within existing design flows,” said Shawn McCloud, VP of Marketing at Calypto. “More customers are moving to C++ or SystemC as an input language for hardware design where verification can be performed more exhaustively and up to 10,000X faster than RTL. Catapult Synthesis delivers the link from these abstract models to RTL, and integrating it with Real Intent’s RTL linter ensures an error-free design flow for today’s complex SoCs.”

“By delivering high performance, capacity and low-noise reporting, Ascent Lint is a state-of-the-art RTL linter and rule checker for full-chip SoC analysis,” said Graham Bell, senior director of Marketing, Real Intent. “Ascent Lint verifies RTL designs in minutes, which is nearly 50X faster than older lint tools. By integrating with Calypto’s synthesis tool, we enable designers to quickly go from ESL to gates, secure in the knowledge that their RTL code meets all of the industry quality standards in their implementation flow.”