Arasan announces MIPI conformant camera serial interface (CSI-3) receiver IP core

USA: Arasan Chip Systems Inc. announced the addition of MIPI Alliance CSI-3 Receiver IP along with a matching Type 1 M-PHY to the company's expansive MIPI portfolio. The CSI-3 Receiver and M-PHY's can be delivered to customers in configurations of 1 to 4 receive lanes.

MIPI's CSI-3 specification is the application layer definition of the latest generation of camera serial interface that utilizes UniPro v. 1.41 as its link layer and the M-PHY v. 2.0 as the physical layer. Like CSI-2, the CSI-3 receiver is meant to deliver its image payload to an on-chip Image Signal Processor (ISP). However, when compared to CSI-2 with D-PHY, the CSI-3/Unipro/M-PHY combination provides higher bandwidth and lower power consumption per bit transferred from a camera module or bridge chip to a receiver in a mobile applications processor.

Over the past two years Arasan has made significant investment in the development and customer adoption of IP's that have direct relevance to CSI-3. For example, UFS is a JEDEC application layer standard for mobile storage which, like CSI-3, leverages UniPro and M-PHY as its lower level protocol stack. Through successful deployment of its market leading UFS solution Arasan has mastered the implementation complexities of the UniPro link layer with its software stack, and the M-PHY across multiple advanced process nodes.

Over the past three years Arasan has been shipping the CSI-2 Receiver IP, which plugs into differing system and ISP bus variants. Such a rich history of product delivery has created a portfolio of mature reusable blocks which, when combined with the new CSI-3 application layer, provide customers the ability to rapidly integrate the CSI-3 receiver capability into applications processors and camera bridge chips.

Arasan offers UniPro v. 1.41 as part of the CSI-3 Receiver IP, which is deliverable in source RTL form with accompanying verification IP targeted for rapid design integration. Arasan's Type 1 M-PHY's, which are licensed separately, are designed to be compatible with the CSI-3/UniPro PHY Adapter layer, with flexibility in data bus widths across the RMMI interface.

Arasan's MIPI CSI-3 Receiver IP Core is available immediately for licensing, including Verilog HDL of the IP Core, Verification IP, synthesis scripts, and documentation. The corresponding M-PHY IP is available as a hard macro targeted to any process node, along with all the customer required support files and documentation.