MOS-AK/GSA modeling working group holds winter workshop in San Francisco

USA: The MOS-AK/GSA Working Group, a global compact modeling standardization forum, has delivered their 5th international compact modeling workshop, organized on Dec. 12, 2012 in the time frame of the IEDM Conference in San Francisco.

The event was organized at swissnex receiving full sponsorship provided by leaders in electronic design automation including Agilent Technologies and Mentor Graphics. The FP7 COMMON Project, Eurotraining, and MOSIS Services were among the workshop technical program promoters. More than 40 international academic researchers and modeling engineers attended two sessions to hear 11 technical compact modeling talks.

The workshop’s two sessions focused on the advances in compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization.

The speakers discussed: “Scaling Challenges of Analog Electronics” (Mustafa Badaroglu, IMEC); “Interactive Modeling and Online Simulation Platform” (Mansun Chan, HKUST); “Nonlinear Device Modeling With Scalable X-Parameters” (David E. Root, Agilent), “PSP Model Update” (Gert-Jan Smit, NXP); “Global Geometrical Scaling in BSIM6” (Yogesh S. Chauhan, IIT Kanpur); “KLU and PSS Implementations in NGSPICE” (Francesco Lannutti, NGSPICE), “GCC Front-End of Compact Modeling Verilog-AMS Language” (Laurent Lemaitre, Noovela); “SPICE Modeling of STT-RAM for Resilient Design” (Zihan Xu, ASU); “Modeling and Parameter Extraction of Zero-VT MOSFETs for Ultra-low-Voltage Operation” (Carlos Galup-Montoro, FUSC); “Charge Trapping Phenomena in MOSFETs” (Gilson Wirth, UFRGS), and “Consistent Parameter Extraction Using Different MOSFET Models” (Luiz Alberto Pasini Melek, FUSC).

The compact modeling panel discussion moderated by Larry Nagel concluded the MOS-AK/GSA workshop. Invited international academic researchers and modeling engineers reviewed the status of compact modeling standardization and agreed that the Verilog-A standard offers a unique platform for compact model developments, validation, exchange and implementation into commercial as well as open source CAD/EDA tools.

The panelists also pointed out the needs of further Verilog-A standard extensions and broader Verilog-AMS language definitions to better support compact device modeling, in particular focusing on Analog/RF noise applications. It is also expected that open source developers will actively contribute to standards promotion, addressing the challenges of related CAD/EDA software developments, such as Verilog-AMS debuggers supporting new model validations; and full featured, integral Verilog-AMS simulators for semiconductor device model benchmarking.