Monday, December 17, 2012

MonolithIC 3D shows 3D-ICs can be effectively cooled

USA: MonolithIC 3D Inc., presented a paper at the IEEE International Electron Devices Meeting (IEDM) showing that effective cooling of 3D-ICs can be made possible by utilizing the circuit’s power delivery networks* (PDNs) and the high density of vertical connections enabled by monolithic 3D stacking. The paper, co-authored with Stanford University, was delivered by doctoral candidate Hai Wei at IEDM in San Francisco, CA on December 11th, 2012, and titled “Cooling Three-Dimensional Integrated Circuits Using Power Delivery Networks".

Heat removal from the stacked layers of 3D ICs has been an industry issue for many years, and has been thought to be a limiter on the types and performance of circuits that can be stacked. As well, hot spots in the stacked layers have been identified as a challenge in 3D integration and stacking. The efficient removal of device generated heat can be exacerbated by the thin silicon layers and islands utilized by the fully depleted (FD) devices that the industry is rapidly moving towards.

Wei and fellow graduate student Tony Wu, part of Professor Subhasish Mitra’s group at Stanford, guided by Prof. Mitra and Professor Fabian Pease, performed a comprehensive analysis that quantifies the impact of PDNs on the thermal profile of 3D ICs over a variety of 3D integration methods, application power densities and temperature constraints, and density of vertical interconnects.

One important result of their comprehensive work was thermal analyses of core-on-core and memory-on-core designs utilizing the OpenSPARC T1. They showed that the processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration.

“We are grateful to Professors Mitra and Pease for their belief in the importance of monolithic-sequential 3D IC and embarking on this important ground breaking research,” says Brian Cronquist, co-author and VP Technology & IP at Monolithic 3D Inc. “Hai and Tony did a thorough job of investigating the influence of the PDNs and the effect of the density and size of the inter-layer vias.”

The paper analyzed the heat removal effects of the sparse and large sized vertical interconnect called Thru Silicon Vias (TSVs) and of the greatly increased density of vertical interconnect afforded by monolithic 3D techniques, which is on the order of millions to tens of millions per square centimeter. An analysis framework has been constructed that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs.

MonolithIC 3D Inc.’s President and CEO, Zvi Or-Bach, said: "We are pleased that our continued innovation efforts and collaboration with Stanford University has achieved an important result for the industry. Monolithic 3D is now not limited by heat as device generated heat can be effectively carried to the heat sink through the properly designed power delivery networks leveraging the dense vertical interconnects enabled by monolithic 3D IC technology.”

The IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. In this year’s conference there is an increased emphasis on circuit and device interaction. Outstanding research results covering design and fabrication of semiconductors, modules and devices are published at IEDM each year. Only 203, out of over 600 submitted, papers have been selected for 2012 IEDM.

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