Cadence Encounter technologies enable Open-Silicon to reach 2.2 GHz performance on 28nm ARM dual-core Cortex-A9 processor

INDIA: Cadence Design Systems Inc. announced that Open-Silicon, Inc., a leading semiconductor design and manufacturing company, has leveraged the latest innovations from the Cadence Encounter RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nanometer hardening of an ARM® dual-core Cortex-A9 processor.

Open-Silicon used the latest Encounter digital RTL-to-signoff products for the processor core which is targeted for mobile computing applications, including RTL Compiler-Physical (RC-Physical) and Encounter Digital Implementation (EDI) System. EDI System features advanced GigaOpt optimization and Clock Concurrent Optimization (CCOpt) technologies, which, together with RC-Physical, helped reduce the design area by 10 percent, clock tree power by 33 percent and overall leakage power by 27 percent compared to a prior flow, while accelerating design closure by two weeks.

Open-Silicon’s chips go into leading-edge products where power, performance, and area (PPA), and time-to-parts are paramount. Open-Silicon’s extensive experience with processor implementations across many verticals, including networking/telecom, storage and computing, enables turnkey ARM technology-based SoC design.

By leveraging the Center of Excellence (CoE) for ARM Technology-based Designs at Open-Silicon and Cadence optimized RTL-to-signoff flows, customers are now able to achieve market-differentiating performance and power efficiencies in their ARM technology-based products.

“Improving designer productivity and time-to-market are absolutely critical to Open-Silicon’s rapid execution of SoC development. The predictability of the Cadence RTL-to-Sign-off flow, which includes excellent convergence from RC-Physical to EDI System and Encounter Timing System (ETS) for sign-off, has enhanced Open-Silicon’s competitive advantage in delivering industry-leading ARM processor-based SoC designs,” said Taher Madraswala, senior vice president of engineering at Open-Silicon.

“Achieving 2.2 GHz under typical conditions on the ARM dual-core Cortex-A9 processor at advanced nodes and in a short turn-around time is a testament to Open-Silicon and Cadence’s capabilities and collaborative efforts. The PPA and runtime improvement as a result of adopting Encounter GigaOpt and CCOpt technologies in our CoE chip design flows is a real game changer.”

The Cadence Encounter RTL-to-signoff flow has been significantly optimized for ARM processor-based design, helping design teams optimize PPA for the world’s most advanced high-performance, and power efficient designs. The flow includes Encounter RC-Physical, EDI System, and signoff-proven Cadence QRC Extraction, and ETS.

The new GigaOpt technology inside EDI System produces high-quality results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the integrated CCOpt technology unifies clock tree synthesis with logic/physical optimization resulting in significant PPA improvements.

As a result of this success, Open-Silicon has standardized on the Encounter RTL-to-signoff flow in its CoE for hardening high-performance ARM technology-based SoCs.

“We congratulate Open-Silicon on this significant achievement, and thank them for partnering with Cadence to optimize PPA for the world’s most sophisticated and complex ARM processor-based designs,” said Dr. Chi-Ping Hsu, senior VP, R&D, Silicon Realization Group at Cadence. “In collaboration with our partners, Cadence is focused intently on enabling customers to implement high-performance processors that power many of today’s popular electronic products.”