Faraday adopts ATopTech’s Aprisa for physical implementation at advanced process nodes

SAN JOSE, USA: ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), announced that Faraday Technology Corp. has adopted ATopTech’s Aprisa physical design solution as the company’s tool of choice for physical implementation at advanced process nodes. Faraday Technology Corp. is one of the largest leading silicon IP and fabless ASIC provider in the Asia-Pacific region.

40nm technology helps design engineers satisfy their customers’ continuous demands of higher performance, lower power consumption and lower manufacturing cost. However, designs at 40nm impose tremendous challenges, such as increased cross-talk effect and process variation, which, if not addressed properly, may cause compromised quality of results and delay in design closure.

It is exactly these areas that Aprisa, ATopTech’s advanced netlist-to-GDSII physical implementation tool, consistently demonstrates: superior routing ability and excellent timing closure. Faraday’s extensive evaluation of Aprisa was further validated when Aprisa delivered better design quality and more predictable design closure with a successful design tapeout in UMC’s 40nm process.

“Complicated physical effects and demanding design specifications present increased challenges for 40nm design projects,” said Kun-Cheng Wu, associate VP of Faraday Technology. “We are pleased with the improved quality of results and turn-around time we’ve gained by adopting Aprisa as our physical implementation tool.”

“ATopTech’s place and route technology was architected specifically for advanced technologies,” said Jue-Hsien Chern, CEO of ATopTech, Inc. “We are fully committed to helping Faraday to achieve further successes in 40nm and other design projects.”