SAN JOSE, USA: Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced the adoption of Atrenta’s latest 4.5 release of its SpyGlass Power and DFT DSM solutions into version 5.0 of the STARCAD-CEL reference flow for RTL estimation, reduction and verification of low power designs. The STARCAD-CEL reference flow is provided by the Semiconductor Technology Academic Research Center (STARC).
“Atrenta’s latest release of power and deep submicron test solutions for RTL power estimation, reduction and verification offer the right answer to address today’s complex design challenges,” said Nobuyuki Nishiguchi, vice president and general manager, R&D Department-2 at STARC. “The version 5.0 of the STARCAD-CEL Reference Flow includes Atrenta’s SpyGlass Power and SpyGlass DFT DSM solutions, enabling our customers to find killer bugs and implement low power design strategies while saving multiple iterations of synthesis and tens of hours of power simulations at the gate level.”
New un-instrumented RTL checks were added to the SpyGlass Power product to support verification of RTL designs with power strategies that enable downstream implementation tools to insert the correct level shifters and isolation logic. The new low-power DFT rules in the SpyGlass DFT DSM product were verified on the STARC design suite with CPF & UPF power intent data. These rules help to verify that correct “test control cells” are added to isolate the power management units (PMU) for scan-based testing. STARC engineers have also conducted an exhaustive evaluation of Atrenta’s CPF & UPF power format support and power intent verification capability on over 100 test case designs with multiple voltage domains and power domains.
STARC evaluated the SpyGlass Power solution with both vectors and vector-less analysis for estimation of leakage power, data path and clock power. The RTL power estimation results of the latest SpyGlass 4.5 release have significantly improved over the previous releases. The power numbers at RTL were within 8.5 percent of gate level numbers with an improved runtime of 16 percent compared to the previous release. About a 40 percent power reduction was achieved on STARC designs with embedded memories by using the latest formal techniques included in the product.
“Atrenta is the only vendor to provide RTL power estimation, reduction and verification support with both CPF and UPF power format support for both design and test modes,” said Kiran Vittal, product marketing director for clocks, power and test products at Atrenta. “STARC’s thorough evaluation and adoption of SpyGlass Power into the STARCAD-CEL flow has once again validated the effectiveness of using early analysis solutions at RTL for both design and test on low power designs.”