ESC Silicon Valley 2011, LEXINGTON, USA: Adapteva, a privately-held semiconductor technology startup, announced its flagship Epiphany microprocessor architecture IP (intellectual property). The company’s technology is unprecedented in its ability to scale to thousands of parallel processors on a single chip, connected through a high-bandwidth on-chip network, with each processor capable of executing separate and independent programs.
The resulting performance boost is coupled with Adapteva’s extremely low-power design and standard C programming model, bringing an unprecedented level of real-time processing to performance- and power-constrained mobile devices like smartphones and tablet computers, as well as improving performance levels for an array of other parallel computing platforms.
The Epiphany architecture shatters all previous commercial multicore achievements. The company has implemented a high performance version of the architecture, featuring 1,000 general-purpose floating point processor cores, an order of magnitude (10x) greater than any previously announced multicore device.
By designing processor and network sub-components specifically for massive multicore processing and for low-power embedded computing, Adapteva was able to remove much of the power inefficiency often seen in traditional microprocessors and networks. The benefits of this technology are far reaching in healthcare, military and high performance computing applications – and on mobile computing devices, the impact is even more pronounced.
While dual- and quad-core processors have entered the mobile market in the past year, Adapteva now enables the integration of a 64-core general-purpose processing engine into the silicon real estate of a typical smartphone System-On-Chip (SoC). Based on recent trends in multicore performance growth and generally accepted industry performance projections, Adapteva’s leap to 64-cores represents a disruptive change in the mobile marketplace that should not have occurred until 2016.
Epiphany’s high performance and low-power consumption makes it ideal for augmenting existing mobile processors (such as ARM), and allows processing-intensive applications, which today must be shipped over the cellular network to a server, to be executed in real-time directly on the mobile device.
“With the Epiphany multicore architecture, the application lag-time inherent in today’s mobile computing environment can become a thing of the past,” said Andreas Olofsson, CEO and founder of Adapteva. “’Real-time’ will have a new meaning for complex mobile-computing capabilities that used to be restricted to the server, but can now be processed locally on the mobile device itself. Applications, from virtual content overlay, to face recognition, to real-time speech recognition, that will be feasible with our truly parallel computing environment, aren’t even envisioned as possible with the newly available quad-core devices.”
“Adapteva’s combination of C-programmability, ease-of-use, built-in floating point support, and unprecedented energy efficiency makes it an ideal accelerator for systems needing to augment existing FPGA-based signal chains with advanced floating-point algorithms,” said Jeff Milrod, president and CEO of BittWare. “At BittWare, we saw the possibilities for the Adapteva technology advance from day one. This is why we chose to OEM Adapteva’s chips on our boards – with its unique capabilities; we will be able to leap far ahead of the competition.”
Adapteva has developed a silicon reference platform in 65nm based on the Epiphany architecture, featuring 16 processor cores running at 1GHz and off-chip links with 8GB/sec total bandwidth. Running the C-based CoreMark benchmark from EEMBC at 1GHz, each one of the processor cores achieves an out-of-the-box benchmark score of 1288, demonstrating the ease-of-use of the Epiphany architecture.
The performance of the reference chip is even more impressive in executing floating-point math programs (high-accuracy), where it demonstrates an energy efficiency of 35 GFLOPS/Watt. Adapteva offers a complete hardware development kit for evaluating the Epiphany architecture and silicon reference design. The kit features a full suite of multicore development tools including an ANSI-C compiler, cycle accurate multicore simulator, debugger, Integrated Development Environment and multicore run-time libraries.