MOS-AK/GSA Modeling Working Group holds Spring Workshop in Paris

SAN JOSE, USA: The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual spring workshop on April 7-8, 2011 at LIP6/ Pierre and Marie Curie University (UPMC) in Paris, France.

More than 60 international academic researchers and modeling engineers attended three sessions to hear 13 technical compact modeling talks and nine poster presentations. The MOS-AK/GSA Modeling Working Group organized the event with the help and full sponsorship of Marie-Minerve Louerat and the LIP6 laboratory within UPMC.

The workshop’s three sessions focused on high-voltage metal-oxide semiconductor (HVMOS) modeling, technology computer-aided design (TCAD)/CAD simulations and advanced compact modeling.

In the HVMOS modeling session, modeling experts presented advances in high-performance HV metal-oxide semiconductor field-effect transistor (MOSFET) modeling at the 40 nanometer CMOS node; reviewed reliability and aging models for HVMOS; introduced extraction of a scalable electrical model for HV (600/800V) MOS transistors; and presented the Swiss Federal Institute of Technology Lausanne (EPFL)-HV MOSFET model for the first time.

The TCAD/CAD simulations session discussed emerging simulation topics concerning open source/GNU CAD tools (the quite universal circuit simulator (QUCS) and NGSpice simulator) and their applications for device-level compact modeling.

Finally, the advanced compact modeling session covered physics-based compact models essential for FinFETs, radio frequency (RF) heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs), and emerging lateral-diffused metal-oxide semiconductor (LDMOS) devices.

The event ended with high-quality technical poster presentations covering compact model development, implementation, deployment, device-level circuit simulations and model standardization.