Panel at Semico summit 2011 to address challenges at 28nm and below

PHOENIX, USA: The semiconductor industry thrives on the types of challenges that inspire innovation, the driving force behind Moore's Law. But the industry, perhaps, has never had to deal with issues like the ones we're facing today.

The leading edge is at 28nm and below. Both technical and business challenges face designers and manufacturers of leading-edge ICs. Semico Research has brought together representatives from the design customer, foundry, EDA tools and high-end IP perspectives into one panel to explore these challenges. The panel is titled "Challenges at 28nm and Below for First-Time Silicon Success," and will be moderated by Mahesh Tirupattur, Executive Vice President of Analog Bits. Panel members include:

* Moderator: Mahesh Tirupattur, Executive Vice President, Analog Bits.
* Chi-Ping Hsu, Ph.D., Senior Vice President, Research and Development, Silicon Realization Group, Cadence.
* Mark Papermaster, Vice President, Switching Silicon Technology Group, Cisco.
* Grant Pierce, President & CEO, Sonics.

The panel will explore the challenge of designing and manufacturing leading edge ICs. The semiconductor market is a fast-moving competitive environment that is increasingly communication and consumer driven with a strong drive to provide increasing performance and bandwidth in a reduced power environment. The panel will discuss the critical issues in coordinating EDA challenges with customer design requirements, challenges in efficiently connecting multi IP blocks and resulting in a manufacturable high yielding IC on time and on budget to hit the market window.