SAN JOSE, USA: PLDA, the industry leader in the high-speed interconnect IP market, announced the immediate availability of their PCI Express (PCIe) 3.0 FPGA IP with complete support for the Xilinx 7 series FPGAs. The PLDA PCIe IP Core is ready for simulation targeting Xilinx 7 series GTX transceivers at Gen3 speed, taking advantage of the flexibility and faster runtimes of Xilinx ISE Design Suite 13 software.
PLDA is a Xilinx Alliance Program Member, providing PCI Express soft IP for a variety of Xilinx FPGA products. The PLDA PCIe 3.0 FPGA cores are highly configurable soft IP products, with the ability to tailor and select features to optimize gate count and reduce the overall footprint. Key features of the PLDA PCIe 3.0 IP Core for Xilinx 7 series include:
* Full data rate support for PCIe Gen3 (8.0 GT/sec), Gen2 (5.0 GT/sec) and Gen1 (2.5 GT/sec) speeds.
* Comprehensive reference designs to deliver a faster and more reliable route to silicon.
* Leading technical support provided directly by the IP design team, ensuring easy integration and first-pass silicon success.
“Our customers are seeking improved productivity as their design cycles continue to be shortened. PLDA’s PCIe 3.0 IP core, which is specifically designed to interface with the GTX transceivers built into our Kintex-7 and Virtex-7 FPGAs, fits into our Plug-and-Play initiative to accelerate customer development cycles.” said Rick Tomihiro, director of IP Marketing at Xilinx. “With AMBA 4 Advanced Extensible Interface (AXI4) support and integration to our CORE Generator tool, cores from PLDA can dramatically enhance design flexibility, speed development time and reduce risk.”
Stephane Hauradou, PLDA’s CTO, added: “With Xilinx leadership in 28nm FPGAs, PLDA continues to be on the leading edge of PCI Express and interface IP design. We see our ability to tailor our IP to integrate with leading products like the Xilinx 7 series FPGAs as a key enabler of design excellence.”