Tuesday, March 8, 2011

TSMC uses Nangate design optimizer and library creator to improve chip implementation performance

SUNNYVALE, USA: Nangate Inc., the leading supplier of digital cell library development and design optimization solutions, announced that TSMC is using Nangate Design Optimizer and Library Creator for chip implementation to achieve improved performance on advanced process nodes.

TSMC uses Nangate Design Optimizer (NDO) an advanced re-synthesis solution, to enable improved design performance as compared to traditional synthesis techniques. NDO integrates seamlessly with the latest generation of physical design flows to achieve improved SoC performance and improved designer productivity.

NDO utilizes a new library set built and validated by Nangate Library Creator standard cell development and characterization platform. Nangate provides a unique capability to create a very large set of fine-grained drive and skew cells together with combined, complex and leakage control cell variants that enable the digital logic of an IP core or SoC design to operate with significantly higher performance than with a traditional standard cell library approach.

“We are very excited to have our advanced design capabilities being used by TSMC,” said Jens Andersen, VP, Worldwide Sales, Nangate. “The Nangate Design Optimization suite of products and Library Creator enable the true performance potential of the latest process technology nodes to be realized as part of a readily deployable design flow.”

“TSMC is committed to supporting TSMC Open Innovation Platform with our partners’ most advanced methodologies and tools that are necessary to deploy the latest designs into leading edge process nodes at 40nm, 28nm and below,” said Suk Lee, Director of Design Infrastructure Marketing at TSMC. “In line with this commitment TSMC has deployed Nangate's products to achieve speed improvements unachievable until now through traditional physical synthesis flows and library IP.”

Nangate and TSMC will continue with their joint efforts to provide the design community with the most advanced design flows and IP to enable customers to maximize design performance across all the advanced process nodes.

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