Cypress intros high-performance buffer family with industry’s lowest jitter

SAN JOSE, USA: Cypress Semiconductor Corp. has introduced a new clock buffer family that offers the industry’s lowest additive RMS phase jitter. The CY2Dx15xx family features additive RMS phase jitter as low as 60fs while delivering propagation delays as low as 480ps.

The new buffers produce multiple identical clocks typically used by several interface ports and ICs such as processors and FPGAs in the system. They can produce up to 10 differential outputs in formats including LVPECL, LVDS, and CML. The new buffers are offered in a variety of packages including 8-pin SOIC, 8-pin TSSOP, 20-pin TSSOP, and 32-pin TQFP.

This family of low-jitter, low-skew high-performance buffers complements Cypress’s FleXO family of low-jitter clock generators. Together with FleXO, the High-Performance Buffer Family can help fulfill the timing tree requirements in a variety of systems, including networking routers, switches, and wireless base stations.

“Our customers told us that jitter is one of the most important aspects of their clock fanout buffer selection,” said Sonal Chandrasekharan, Business Unit Manager for Cypress Timing Solutions. “Our new High-Performance Buffer family offers the industry’s lowest jitter and combines with our FleXO devices to deliver clock trees with excellent timing margins.”

The High-Performance Buffers are available today from Cypress and its authorized distributors.